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PM5366-PI Datasheet(PDF) 239 Page - PMC-Sierra, Inc |
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PM5366-PI Datasheet(HTML) 239 Page - PMC-Sierra, Inc |
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239 / 267 page ![]() PRELIMINARY PM5366 TEMAP-84 DATASHEET PMC-2010672 ISSUE 1 HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER PROPRIETARY AND CONFIDENTIAL 227 Figure 42: Microprocessor Interface Read Timing INTB tZINTH (CSB+RDB) Valid Data D[7:0] tPRD tZRD tSAR tH AR Valid Address A[12:0] ALE tS ALR tVL tS LR tHALR tHLR Notes on Microprocessor Interface Read Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface data bus, (D[7:0]). 3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals. 4. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALR, tHALR, tVL, and tSLR are not applicable. |
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