PM5366-PI datasheet(127/267 Pages) PMC

127 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

115

9.37 Microprocessor Interface

The Microprocessor Interface Block provides normal and test mode registers, the

interrupt logic, and the logic required to connect to the Microprocessor Interface.

The normal mode registers are required for normal operation, and test mode

registers are used to enhance the testability of the TEMAP-84.

The Register Memory Map in Table 9 shows where the normal mode registers

are accessed. The resulting register organization splits into sections: Master

configuration registers, T1/E1 registers, DS3 M13 multiplexing registers,

SONET/SDH mapping registers and SBI registers.

On power up reset the TEMAP-84 defaults to 1.544 kbit/s tributaries multiplexed

into the three M13 multiplexers using the DS3 M23 multiplex format. For proper

operation some register configuration is necessary. System side access defaults

to the SBI bus without any tributaries enabled which will leave the SBI Drop bus

tristated. By default interrupts will not be enabled, automatic alarm generation is

disabled, a dual rail DS3 LIU interface is expected and an external transmit

reference clock is required.

Table 9

- Register Memory Map

Address

0x0000

Revision

0x0001

Global Reset

0x0002

Global Configuration

0x0003

SPE #1 Configuration

0x0004

SPE #2 Configuration

0x0005

SPE #3 Configuration

0x0006

Bus Configuration

0x0007

Global Performance Monitor Update

0x0008

Reference Clock Select

0x0009

Recovered Clock#1 Select

0x000A

Recovered Clock#2 Select

0x000B

Recovered Clock#3 Select

PM5366-PI Datasheet(PDF) 127 Page - PMC-Sierra, Inc

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