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PM5366-PI Datasheet(PDF) 152 Page - PMC-Sierra, Inc |
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PM5366-PI Datasheet(HTML) 152 Page - PMC-Sierra, Inc |
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152 / 267 page ![]() PRELIMINARY PM5366 TEMAP-84 DATASHEET PMC-2010672 ISSUE 1 HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER PROPRIETARY AND CONFIDENTIAL 140 Register 0x1000: Master Test Register Bit Type Function Default Bit 7 R/W Reserved 0 Bit 6 Unused X Bit 5 Unused X Bit 4 R/W PMCTST 0 Bit 3 W DBCTRL X Bit 2 R/W Reserved 0 Bit 1 W HIZDATA X Bit 0 R/W HIZIO 0 This register is used to select TEMAP-84 test features. All bits, except for PMCTST, are reset to zero by a hardware reset of the TEMAP-84; a software reset of the TEMAP-84 does not affect the state of the bits in this register. PMCTST: The PMCTST bit is used to configure the TEMAP-84 for PMC's manufacturing tests. When PMCTST is set to logic 1, the TEMAP-84 microprocessor port becomes the test access port used to run the PMC "canned" manufacturing test vectors. The PMCTST bit can only be cleared by setting CSB to logic 1. DBCTRL: The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin while PMCTST is a logic 1. When the DBCTRL bit is set to logic 1, the CSB pin controls the output enable for the data bus. While the DBCTRL bit is set, holding the CSB pin high causes the TEMAP-84 to drive the data bus and holding the CSB pin low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads. When PMCTST is logic 0, the DBCTRL bit is ignored. Reserved: These bits must be logic 0 for correct operation. |
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