PM6388 datasheet(39/345 Pages) PMC

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PM6388 EOCTL

DATA SHEET

PMC-1971019

ISSUE 6

OCTAL E1 FRAMER

PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use

INTB

Output

Active low open-drain Interrupt signal (INTB). This

signal goes low when an unmasked interrupt event is

detected on any of the internal interrupt sources.

Note that INTB will remain low until all active,

unmasked interrupt sources are acknowledged at

their source.

CSB

Input

Active low chip select (CSB). This signal must be

low to enable EOCTL register accesses.

CSB must

go high at least once after a powerup to clear internal

test modes. If CSB is not used, then it should be tied

to an inverted version of RSTB, in which case, RDB

and WRB determine register accesses.

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

I/O

Bidirectional data bus (D[7:0]). This bus is used

during EOCTL read and write accesses.

RDB

Input

Active low read enable (RDB). This signal is pulsed

low to enable a EOCTL register read access. The

EOCTL drives the D[7:0] bus with the contents of the

addressed register while RDB and CSB are both low.

WRB

Input

Active low write strobe (WRB). This signal is pulsed

low to enable a EOCTL register write access. The

D[7:0] bus contents are clocked into the addressed

normal mode register on the rising edge of WRB

while CSB is low.

ALE

Input

Address latch enable (ALE). This signal latches the

address bus contents, A[10:0], when low, allowing the

EOCTL to be interfaced to a multiplexed address/data

bus. When ALE is high, the address latches are

transparent. ALE has an integral pull-up.

RSTB

Input

Active low reset (RSTB). This signal is set low to

asynchronously reset the EOCTL. RSTB is a

Schmitt-trigger input with integral pull-up. When

resetting the device, RSTB must be asserted for a

minimum of 100 ns to ensure that the EOCTL is

completely reset.

PM6388 Datasheet(PDF) 39 Page - PMC-Sierra, Inc

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