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PM6388 Datasheet(PDF) 79 Page - PMC-Sierra, Inc |
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PM6388 Datasheet(HTML) 79 Page - PMC-Sierra, Inc |
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79 / 345 page  PM6388 EOCTL DATA SHEET PMC-1971019 ISSUE 6 OCTAL E1 FRAMER PROPRIETARY and CONFIDENTIAL to PMC-Sierra Inc. and for its customers’ internal use 60 multiframe alignment must be provided on CEFP by setting FPTYP bit of the Transmit Backplane Frame Pulse Configuration register to logic 1. Otherwise, the identification of the incoming CRC-4 bits would be impossible. The PATHCRC bit only takes effect when the INDIS or FDIS bit of the TRAN Configuration register is logic 1. EFPRISE : The EFPRISE bit enables the egress frame pulse to be updated on the rising CECLK edge. When EFPRISE is set to logic 1, EFP[x] is updated on the rising CECLK edge. When EFPRISE is set to logic 0, EFP[x] is updated on the falling CECLK edge. This register bit is only active when Clock Slave: EFP Enabled mode is selected. TLCLKRISE: The TLCLKRISE bit enables the transmit line interface to be updated on the rising TLCLK[x] edge. When TLCLKRISE is set to logic 1, TLD[x] is updated on the rising TLCLK[x] edge. When TLCLKRISE is set to logic 0, TLD[x] is updated on the falling TLCLK[x] edge. |
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