PM6541 datasheet(10/49 Pages) PMC

10 / 49 page

PMC-Sierra, Inc.

PM6541 E1XC-EVBD

TELECOM STANDARD PRODUCT

PMC-930917

ISSUE 1

E1XC EVALUATION DAUGHTERBOARD

AD[1]

I/O

C19

Multiplexed address/data bus bit 1

AD[0]

I/O

C20

Multiplexed address/data bus bit 0

PA3

C21

68HC11 Processor Port A bit 3

PA4

C22

68HC11 Processor Port A bit 4

PA5

C23

68HC11 Processor Port A bit 5

PA6

C24

68HC11 Processor Port A bit 6

PD2

C25

MISO. Master In Slave Out of Port D acting as SPI.

Pulled up on motherboard.

PD3

C26

MOSI. Master Out Slave In of Port D acting as SPI.

Pulled up on motherboard.

PD4

C27

SCK. Serial clock of Port D acting as SPI. Pulled up

on motherboard.

PD5

C28

SS. Slave Select of Port D acting as SPI active low.

Pulled up on motherboard.

IRQ

C29

Maskable interrupt

XIRQ

C30

Non Maskable Interrupt

DISB

C31

EVMB memory disable. Pulling this signal low will

disable MPU access to the EVMB's on-board RAM

and EPROM.

C32

SPARE

GND

A1-

A28

Ground

+5V

A29-

A32

+5 Volts

3.2

Header Connections

All E1XC functional pins are connected to male header strips to provide as much

access as possible. These headers may be used as probe points or as a means to

build sample applications by making appropriate connections between points. Each

E1XC can run in isolation of the other, thus any application, other than the default

sample "CSU", will require header connections to be made.

PM6541 Datasheet(PDF) 10 Page - PMC-Sierra, Inc

PM6541 Datasheet(HTML) 10 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL