PM7344 datasheet(66/293 Pages) PMC

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PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

format) or 6.6 Hz (for the T1 formats) are attenuated by 6 dB per octave of jitter

frequency. Phase variations below these jitter frequencies are tracked by

TCLKO.

Jitter Characteristics

The DJAT provides excellent jitter tolerance and jitter attenuation while

generating minimal residual jitter. It can accommodate up to 28 UIpp of input

jitter at jitter frequencies above 6 Hz for T1 interfaces or 9 Hz (for E1 interfaces).

For jitter frequencies below 6/9 Hz, more correctly called wander, the tolerance

increases 20 dB per decade. In most applications DJAT will limit jitter tolerance

at lower jitter frequencies only. The DJAT block meets the low frequency jitter

tolerance requirements of AT&T TR 62411 for T1 interfaces, and ITU-T G.823 for

E1 interfaces.

Outgoing jitter may be dominated by the generated residual jitter in cases where

the incoming jitter is insignificant. This residual jitter is directly related to the use

of the 24x clock for the digital phase locked loop.

For T1 interfaces, DJAT meets the jitter attenuation requirements of AT&T TR

62411. DJAT meets the implied jitter attenuation requirements for a TE or an

NT1 specified in ANSI T1.408, and for a type II customer interface specified in

ANSI T1.403.

For E1 interfaces, DJAT meets the jitter attenuation requirements of ITU-T

Recommendations G.737, G.738, G.739, and G.742.

Jitter Tolerance

Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a

device can accept without exceeding its linear operating range, or corrupting

data. For DJAT, the input jitter tolerance is 29 Unit Intervals peak-to-peak (UIpp)

for a T1 interface with a worst case frequency offset of 354 Hz. The input jitter

tolerance is 35 UIpp for an E1 interface with a worst case frequency offset of 308

Hz. It is 48 UIpp with no frequency offset. The frequency offset is the difference

between the frequency of XCLK divided by 24 and that of the input data clock.

These tolerances are shown in Figure 9 and Figure 10 below:

PM7344 Datasheet(PDF) 66 Page - PMC-Sierra, Inc