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ADAQ7980 Datasheet(PDF) 8 Page - Analog Devices

Part # ADAQ7980
Description  Quad, 14-Bit, 4 MSPS, Simultaneous Sampling, μModule Data Acquisition Solution
PDF  45 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADAQ7980 Datasheet(HTML) 8 Page - Analog Devices

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Data Sheet
ADAQ4381-4
SPECIFICATIONS
analog.com
Rev. 0 | 8 of 45
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 3.3 V, TA = −40°C to +105°C, CLOAD_SDO = 30 pF, unless otherwise noted.
Table 3. Digital Interface Timing
Parameter
Min
Typ
Max
Unit
Description
tCYC
250
ns
Time between conversions
tSCLKED
5
ns
CS falling edge to first SCLK falling edge
tSCLK
12.5
ns
SCLK period
tSCLKH
5.5
ns
SCLK high time
tSCLKL
5.5
ns
SCLK low time
tCSH
10
ns
CS pulse width
tQUIET
10
ns
Interface quiet time prior to conversion
tSDOEN
CS low to SDOx enabled
5.5
ns
VLOGIC > 1.75 V
7.6
ns
VLOGIC < 1.75 V
tSDOH
3
ns
SCLK rising edge to SDOx hold time
tSDOS
SCLK rising edge to SDOx setup time
5.5
ns
VLOGIC > 2.1 V
7.5
ns
1.65 V < VLOGIC < 2.1 V
tSDOT
8
ns
CS rising edge to SDOx high impedance
tSDIS
4
ns
SDI setup time prior to SCLK falling edge
tSDIH
4
ns
SDI hold time after SCLK falling edge
tSCLKCS
0
ns
SCLK rising edge to CS rising edge
tCONVERT
190
ns
Conversion time
tACQUIRE
110
ns
Acquire time
tRESET
250
ns
Valid time to start conversion after soft reset
800
ns
Valid time to start conversion after hard reset
tPOWER-UP
Supply active to conversion
5
ms
First conversion allowed
5
ms
Settled to within 1%
tREGWRITE
5
ms
Supply active to register read write access allowed
tSTARTUP
Exiting shutdown mode to conversion
10
μs
Settled to within 1%
tCONVERT0
6
8
10
ns
Conversion time for first sample in OS normal mode
tCONVERTx
tCONVERT0+ 250× x−1 ns ConversiontimeforxthsampleinOSnormalmode
tALERTS
220
ns
Time from CS to ALERT indication
tALERTC
10
ns
Time from CS to ALERT clear
tALERTS_NOS
20
ns
Time from internal conversion with exceeded threshold to ALERT indication



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