Tel: 886-2-66296288

Fax: 886-2-29174598

URL: http://www.princeton.com.tw

PT6520 V1.6

- 22 -

February, 2006

LCD Driver IC

PT6520

READ/WRITE TIMING FOR THE 68-PORT MPU

(Ta=25℃, VDD=0V, VSS=-5V)

Parameter

Signal

Symbol

Condition

Min. Typ. Max Unit

VSS=-5V

1000

-

-

ns

System cycle time

tCYC6

VSS=-3V

2000

-

-

ns

VSS=-5V

20

-

-

ns

Address set-up time

tAW6

VSS=-3V

40

-

-

ns

VSS=-5V

10

-

-

ns

Address hold time

A0, CS

R/W

tAH6

VSS=-3V

30

-

-

ns

VSS=-5V

80

-

-

ns

Control pulse width

tDS6

VSS=-3V

160

-

-

ns

VSS=-5V

10

-

-

ns

Data set-up time

tDH6

VSS=-3V

20

-

-

ns

CL=100pF

VSS=-5V

10

-

60

ns

Data hold time

tOH6

CL=100pF

VSS=-3V

20

-

120

ns

CL=100pF

VSS=-5V

-

-

90

ns

RD access time

D0~D7

tACC6

CL=100pF

VSS=-3V

-

-

180

ns

VSS=-5V

100

-

-

ns

READ

VSS=-3V

200

-

-

ns

VSS=-5V

80

-

-

ns

Enable disable time

WRITE

E

tew

VSS=-3V

160

-

-

ns

Note:

1. tCYC6 indicates the cycle during which CS/E are high; it does not indicate are cycle of the E signal.

CONTROL TIMING FOR 80-PORT/68-PORT MPU

(Ta=25℃, VDD=0V, VSS=-5V)

Parameter

Signal

Symbol

Condition

Min. Typ. Max

Unit

VSS=-5V

1

-

750

µs

Reset time

RES

tR

VSS=-3V

1.5

-

1000

µs

VSS=-5V

1

-

-

µs

Reset time

(68-Port)

RES

tR1

VSS=-3V

1.5

-

-

µs

VSS=-5V

1

-

-

µs

Reset time

(80-Port)

RES

tR2

VSS=-3V

1.5

-

-

µs

Note:

1. The input timing of the FR delay time is determined by the PT6520 (Slave)

2. The output timing of the FR delay time is determined by the PT6520 (Master)