DS06-20206-5E

FUJITSU SEMICONDUCTOR

DATA SHEET

Copyright©1999-2007 FUJITSU LIMITED All rights reserved

Semicustom

CMOS

Standard cell

CS81 Series

■ DESCRIPTION

The CS81 series 0.18

µm CMOS standard cell is a line of highly integrated CMOS ASICs featuring high speed

and low power consumption.

This series incorporates up to 40 million gates which have a gate delay time of 11 ps, resulting in both integration

and speed about three times higher than conventional products.

In addition, CS81 can operate at a power-supply voltage of down to 1.1 V, substantially reducing power consump-

tion.

■ FEATURES

• Technology

: 0.18

µm silicon-gate CMOS, 3- to 6-layer wiring capable of integrating a mixture of high-

speed processes and cells on a single chip (under development)

• Supply voltage

:

+1.8 V ± 0.15 V (normal) to +1.1 V ± 0.1 V

• Junction temperature range :

−40 to +125 °C

• Gate delay time

= 11 ps (1.8 V, inverter, F/O = 1)

= 5 nW/MHz/BC (1.1 V, 2-NAND, F/O = 1)

• Support for high speed (62.2 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps) interface macros for transmission

• Output buffer cells with noise reduction circuits

• Inputs with on-chip input pull-up/pull-down resistors (33 k

Ω typical) and bidirectional buffer cells

• Buffer cells dedicated to crystal oscillators

• Special interfaces (P-CML, LVDS, PCI, AGP, USB, SDRAM-I/F, SSTL, and others. including those under

development)

• IP macros (CPU (FR, ARM7, ARM9), DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others. including

those under development)

• Capable of incorporating compiled cells (RAM/ROM/multiplier, and others.)

• Configurable internal bus circuits

• Advanced hardware/software co-design environment

• Short-term development using a timing driven layout tool

• Support for static timing sign-off

Dramatically reducing the time for generating test vectors for timing verification and the simulation time

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