CS81 Series

2

(Continued)

• Hierarchical design environment for supporting large-scale circuits

• Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) ,

supporting development with minimized timing trouble after trial manufacture

• Support for memory (RAM/ROM) SCAN

• Support for memory (RAM) BIST

• Support for boundary SCAN

• Support for path delay test

• A variety of package options (TQFP, HQFP, EBGA, FBGA, TAB-BGA, FCBGA, LQFP)

■ MACRO LIBRARY (Including macros being prepared)

1.

Logic cells (about 400 types)

2.

IP macros

3.

Special I/O interface macros

• Adder

• Decoder

•AND-OR Inverter

•Non-SCAN Flip Flop

•Clock Buffer

•Inverter

•Latch

•Buffer

•NAND

• OR-AND

•AND

•OR-AND Inverter

•NOR

•OR

• SCAN Flip Flop

• Selector

•ENOR

• BUS Driver

•AND-OR

•EOR

•Others

CPU/DSP

FR, SPARClite, ARM7, ARM9, Communications DSP, DSP for AV

and others

High speed interface macros

622 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps

Interface macro

PCI, IEEE1394, USB, IrDA, and others

Multimedia processing macros

JPEG, MPEG, and others

Mixed signal macros

ADC, DAC, OPAMP, and others

Compiled macros

RAM, ROM, multiplier, adder, multiplier-accumulator, and others

PLL

Analog PLL, digital PLL

• T-LVTTL

• SSTL

• HSTL

• P-CML

• LVDS

• PCI

• AGP

• USB

• IEEE1394

• SDRAM-I/F