ADF4382 datasheet(34/83 Pages) AD

34 / 83 page

Data Sheet

ADF4382

APPLICATIONS INFORMATION

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Rev. 0 | 34 of 83

Standard Power-Up and Initialization

Sequence, Automatic VCO Calibration

The following standard power-up and initialization sequence is the

recommended procedure to power up and program the ADF4382:

1. Follow Step 1 through Step 5 in the Power-Up and Initialization

Sequence section.

2. It is optional to monitor the status of the VCO calibration bits,

ADC_BUSY and FSM_BUSY (Register 0x058, Bit 2 and Bit 1,

respectively. A VCO calibration is completed when ADC_BUSY

transitions from high to low followed by FSM_BUSY transition-

ing from high to low.

3. After the VCO calibration is complete, disable the VCO

calibration clocks by setting EN_DRCLK = EN_DNCLK =

EN_ADC_CLK = 0. Disabling the VCO calibration clocks re-

duces unwanted spurious content.

4. The PLL is locked when the lock detector sets the LKDET pin

(Pin 27) and the LOCKED bit (Register 0x58, Bit 0) high.

5. When changing the frequency, take the following steps:

a. Program only the modified registers.

b. Write to Register 0x010 to start a new VCO autocalibration

as the final step whether it is modified or not.

Fast Power-Up and Initialization, Manually

Programmed VCO Calibration Settings

For fast frequency hopping applications, much shorter lock time is

required. The ADF4382 can be manually programmed with prede-

termined calibration values to decrease overall lock time by bypass-

ing VCO calibration. The calibration values are first obtained by

performing an autocalibration and reading back the corresponding

band, core, and bias values for a given frequency. These values

can then be manually programmed to the ADF4382 on subsequent

device initializations. The values of the readbacks vary with each

device due to process variation.

The following steps outline the procedure to perform a manual VCO

calibration after initialization:

1. Perform an autocalibration with the target frequency required.

2. Read back and record the VCO_CORE and VCO_BAND.

3. If VCO_CORE = 0, read the VCO bias value from

VCO0_BIAS_RDBK. If VCO_CORE = 1, read the VCO bias

value from VCO1_BIAS_RDBK. The value read is used as the

M_VCO_BIAS value.

4. On subsequent power-up and initialization sequences, pro-

gram the override (O_VCO_CORE, O_VCO_BAND, and

O_VCO_BIAS) and manual VCO bits (M_VCO_CORE,

M_VCO_BAND, and M_VCO_BIAS) as documented in Table

24.

5. Program fractional N-divider bit field values as required. See

Output Frequency for calculation.

6. Program N_INT value (Register 0x010) to program all manually

calibrated values.

7. Repeat the sequence for each target frequency.

Note: When going from an integer to a fractional (or fractional to

integer) RF output frequency, after the N_INT register has been

written to, MUTE_NCLK must be set to 1 and then to 0.

Table 24. Manually Programmed VCO Calibration Settings

Bit Fields

Value

Description

O_VCO_DB

0x1

Manually calibrated values are dou-

ble buffered by programming N_INT.

EN_AUTOCAL

0x0

Disables autocalibration.

EN_DRCLK

0x0

Disables DIV_RCLK to the digital

block.

EN_DNCLK

0x0

Disables DIV_NCLK to the digital

block.

EN_ADC_CLK

0x0

Disables the ADC clock.

O_VCO_CORE

0x1

Overrides the VCO core with value in

M_VCO_CORE.

O_VCO_BAND

0x1

Overrides the VCO band with

M_VCO_BAND.

O_VCO_BIAS

0x1

Overrides the VCO bias with

M_VCO_BIAS.

M_VCO_CORE

Program with re-

corded values

Selects the VCO core when

O_VCO_CORE = 1.

M_VCO_BAND

Program with re-

corded values

Selects the band within the core

when O_VCO_BAND = 1.

M_VCO_BIAS

Program with re-

corded values

Selects the bias value used when

O_VCO_BIAS = 1.

N_INT

N-divider integer

word

Programs the double buffered man-

ually calibrated values when written.

MUTE_NCLK

0x1

Mutes the clock signal from the N-di-

vider block to the PFD. MUTE_NCLK

must only be set to 1 and then to

0 when going from an integer to a

fractional frequency or fractional to

integer frequency.

Fast Calibration

The fast calibration feature enables a VCO calibration time of <1 μs

for each output frequency change, by storing 32 discrete VCO core,

band, and bias values across the octave range of the ADF4382.

Fast calibration can be initiated during device initialization. When

fast calibration is started, autocalibration is performed at 32 out-

put frequencies across the octave output frequency range of the

ADF4382. An on chip look-up table in the device register map is

used to store the corresponding VCO core, band, and bias value for

each output frequency.

After initialization, subsequent output frequency changes utilize

the previously stored look-up table to determine the optimal VCO

ADF4382 Datasheet(PDF) 34 Page - Analog Devices

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