ADF4382 datasheet(39/83 Pages) AD

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Data Sheet

ADF4382

APPLICATIONS INFORMATION

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Rev. 0 | 39 of 83

Timed Synchronization Method

The timed synchronization method uses an external synchroniza-

tion signal to synchronize multiple ADF4382 devices, which is the

more traditional method for synchronization of devices. This method

requires an additional external signal from the clock distribution

device to provide the synchronization signal. Each synchronization

signal must be matched for accurate output phase matching. A

rising edge of the synchronization pulse on the SYNC pin of the

ADF4382 triggers the start of the synchronization process, which

then puts the device into a reset state. On the falling edge of the

synchronization pulse, the RFOUT signal phase on each ADF4382

is then aligned to a known phase relative to the reference phase.

The following steps outline the procedure to perform a timed syn-

chronization with two ADF4382 devices in the configuration shown

in Figure 80:

1. Set up the HMC7044B as follows:

a. Set the channels used as a reference to the ADF4382 to

asynchronous mode (for example, set Register 0x00C8 to

0xF3 for Channel 0).

b. Set the divider ratio of the reference channels to 16 for a

reference frequency of 250 MHz (for example, set Register

0x00C9 for Channel 0).

c. Set the channels used as a SYNC signal to the ADF4382 to

dynamic mode (for example, set Register 0x00D2 to 0xFF).

d. Set the divider ratio of the SYNC channels to 8.

e. Set the SYSREF timer (Register 0x005B and Register

0x005C ) value of the HMC7044B the same as the divider

value of the SYNC channels.

f. Set the pulse mode selection to pulse (set Register 0x005A

to 0x01).

g. Send a reseed request to start the references by setting the

reseed request to 1 and then 0 by setting Register 0x001 to

0x80 then setting to 0x00.

2. Set up the ADF4382 as follows:

a. Set TIMED_SYNC (Register 0x01E, Bit 5) = 1.

b. Set EN_REF_RST (Register 0x01E, Bit 6) = 1.

c. Set EN_PHASE_RESYNC (Register 0x01E, Bit 7) = 1.

d. Set SYNC_SEL (Register 0x053, Bit 5) = 0.

e. Set R_DIV (Register 0x020, Bits[5:0]) = 4.

f. Set EN_DRCLK (Register 0x02D, Bit 6) = 1.

g. Verify that the ADF4382 devices are locked.

3. Synchronize both ADF4382 devices as follows:

a. Verify that both ADF4382 outputs are not synchronized.

b. Send a pulse generator request to the HMC7044B by tog-

gling Register 0x001 data from 0x04 to 0x00.

c. Verify that both outputs on both ADF4382 devices is now

phase synchronized.

Figure 80. Timed Synchronization Configuration

PHASE SYNCHRONIZATION SETTINGS

To optimize phase noise and spurious performance on the

ADF4382, there are a number of bit fields that must be program-

med based on the fPFD used. Table 26 shows the optimal settings

for phase synchronization.

Table 26. Phase Synchronization Settings

PFD Frequency

RDIV = 3, 6, 12, 14, 15, 24, 26 to 31, 46, 48 to 63

RDIV = 1, 2, 4, 5, 7 to 11, 13, 16 to 23, 25, 32 to 45, 47

REF_CK_FALL

REF_DC_SEL

xx_DEL1

REF_CK_FALL

REF_DC_SEL

xx_DEL1

fPFD ≥ 225 MHz

200 MHz ≤ fPFD < 225 MHz

148 MHz ≤ fPFD < 200 MHz

130 MHz ≤ fPFD < 148 MHz

85 MHz ≤ fPFD < 130 MHz

fPFD < 85 MHz

1 xx_DEL denotes SYNC_DEL, DNCLK_DEL, and DRCLK_DEL.

ADF4382 Datasheet(PDF) 39 Page - Analog Devices

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