S5935 datasheet(4/204 Pages) AMCC

4 / 204 page

S5935 – PCI Product

DS1527

AMCC Confidential and Proprietary

Revision 1.02 – June 27, 2006

Data Book

TABLE OF CONTENTS

FEATURES .............................................................................................................................................................. 3

APPLICATIONS ...................................................................................................................................................... 3

DESCRIPTION ........................................................................................................................................................ 3

TABLE OF CONTENTS .......................................................................................................................................... 4

LIST OF FIGURES .................................................................................................................................................. 9

LIST OF TABLES .................................................................................................................................................. 12

S5935 ARCHITECTURE ....................................................................................................................................... 14

S5935 Register Architecture ............................................................................................................................ 14

PCI Configuration Registers ............................................................................................................................ 15

PCI Operation Registers .................................................................................................................................. 15

Add-On Bus Operation Registers .................................................................................................................... 16

Non-Volatile Memory Interface ........................................................................................................................ 16

Mailbox Operation ........................................................................................................................................... 17

Pass-Thru Operation ....................................................................................................................................... 19

FIFO PCI Bus Mastering Operation ................................................................................................................. 19

Signal Type Definition ...................................................................................................................................... 23

NON-VOLATILE MEMORY INTERFACE SIGNALS ............................................................................................ 27

ADD-ON BUS INTERFACE SIGNALS .................................................................................................................. 28

PCI CONFIGURATION REGISTERS .................................................................................................................... 32

VENDOR IDENTIFICATION REGISTER (VID) ..................................................................................................... 34

DEVICE IDENTIFICATION REGISTER (DID) ....................................................................................................... 35

PCI COMMAND REGISTER (PCICMD) ................................................................................................................ 36

PCI STATUS REGISTER (PCISTS) ...................................................................................................................... 38

REVISION IDENTIFICATION REGISTER (RID) ................................................................................................... 40

CLASS CODE REGISTER (CLCD) ....................................................................................................................... 41

CACHE LINE SIZE REGISTER (CALN) ............................................................................................................... 45

LATENCY TIMER REGISTER (LAT) .................................................................................................................... 46

HEADER TYPE REGISTER (HDR) ....................................................................................................................... 47

BUILT-IN SELF-TEST REGISTER (BIST) ............................................................................................................ 48

BASE ADDRESS REGISTERS (BADR) ............................................................................................................... 49

Determining Base Address Size ...................................................................................................................... 49

Assigning the Base Address ............................................................................................................................ 49

EXPANSION ROM BASE ADDRESS REGISTER (XROM) ................................................................................. 53

INTERRUPT LINE REGISTER (INTLN) ................................................................................................................ 55

INTERRUPT PIN REGISTER (INTPIN) ................................................................................................................. 56

MINIMUM GRANT REGISTER (MINGNT) ............................................................................................................ 57

MAXIMUM LATENCY REGISTER (MAXLAT) ...................................................................................................... 58

OUTGOING MAILBOX REGISTERS (OMB) ........................................................................................................ 61

INCOMING MAILBOX REGISTERS (IMB) ........................................................................................................... 61

FIFO REGISTER PORT (FIFO) ............................................................................................................................. 61

PCI CONTROLLED BUS MASTER WRITE ADDRESS REGISTER (MWAR) ..................................................... 62

S5935 Datasheet(PDF) 4 Page - Applied Micro Circuits Corporation

S5935 Datasheet(HTML) 4 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL