S5935 datasheet(5/204 Pages) AMCC

5 / 204 page

S5935 – PCI Product

Revision 1.02 – June 27, 2006

AMCC Confidential and Proprietary

DS1527

Data Book

PCI CONTROLLED BUS MASTER WRITE TRANSFER COUNT REGISTER (MWTC) ..................................... 63

PCI CONTROLLED BUS MASTER READ ADDRESS REGISTER (MRAR) ....................................................... 64

PCI CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC) ........................................ 65

MAILBOX EMPTY FULL/STATUS REGISTER (MBEF) ....................................................................................... 66

INTERRUPT CONTROL/STATUS REGISTER (INTCSR) .................................................................................... 68

MASTER CONTROL/STATUS REGISTER (MCSR) ............................................................................................ 72

ADD-ON BUS OPERATION REGISTERS ............................................................................................................ 76

ADD-ON INCOMING MAILBOX REGISTERS (AIMBX) ....................................................................................... 77

ADD-ON OUTGOING MAILBOX REGISTERS (AOMBX) .................................................................................... 77

ADD-ON FIFO REGISTER PORT (AFIFO) ........................................................................................................... 77

ADD-ON CONTROLLED BUS MASTER WRITE ADDRESS REGISTER (MWAR) ............................................ 78

ADD-ON PASS-THRU ADDRESS REGISTER (APTA) ........................................................................................ 79

ADD-ON PASS-THRU DATA REGISTER (APTD) ............................................................................................... 79

ADD-ON CONTROLLED BUS MASTER READ ADDRESS REGISTER (MRAR) ............................................... 80

ADD-ON EMPTY/FULL STATUS REGISTER (AMBEF) ......................................................................................81

ADD-ON INTERRUPT CONTROL/STATUS REGISTER (AINT) .......................................................................... 83

ADD-ON GENERAL CONTROL/STATUS REGISTER (AGCSTS) ...................................................................... 86

ADD-ON CONTROLLED BUS MASTER WRITE TRANSFER COUNT REGISTER (MWTC) ............................. 89

ADD-ON CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC) ............................... 90

INITIALIZATION .................................................................................................................................................... 92

PCI RESET ............................................................................................................................................................ 92

LOADING FROM BYTE-WIDE NV MEMORIES ................................................................................................... 92

PCI BUS CONFIGURATION CYCLES .................................................................................................................. 95

EXPANSION BIOS ROMS .................................................................................................................................... 97

PCI BUS INTERFACE ......................................................................................................................................... 100

PCI BUS TRANSACTIONS ................................................................................................................................. 100

PCI BURST TRANSFERS ................................................................................................................................... 102

PCI Read Transfers ....................................................................................................................................... 102

PCI Write Transfers ....................................................................................................................................... 104

Master-Initiated Termination .......................................................................................................................... 105

Normal Cycle Completion .............................................................................................................................. 105

Initiator Preemption ....................................................................................................................................... 106

Master Abort .................................................................................................................................................. 107

Target-Initiated Termination .......................................................................................................................... 107

Target Disconnects ........................................................................................................................................ 108

Target Requested Retries ............................................................................................................................. 109

Target Aborts ................................................................................................................................................. 109

PCI BUS MASTERSHIP ...................................................................................................................................... 111

Bus Mastership Latency Components ........................................................................................................... 111

Bus Arbitration ............................................................................................................................................... 111

Bus Acquisition .............................................................................................................................................. 112

Target Latency ............................................................................................................................................... 112

Target Locking ............................................................................................................................................... 112

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