S5935 datasheet(77/204 Pages) AMCC

77 / 204 page

S5935 – PCI Product

Revision 1.02 – June 27, 2006

AMCC Confidential and Proprietary

DS1527

Data Book

ADD-ON INCOMING MAILBOX REGISTERS (AIMBX)

Add-On Incoming Mailboxes

1-4

These four DWORD registers provide a method for receiving

data, commands, or command parameters from the PCI

interface. Add-On read operations to these registers may be

in any width (byte, word, or DWORD). These registers are

read-only. Writes to this address space have no effect.

Reading from one of these registers can optionally cause a

PCI bus interrupt (if desired) when the PCI interrupt control/

status register is properly configured.

Add-On Address Offset

00h, 04h, 08h, 0Ch

Power-up value

XXXXXXXXh

Attribute

Read Only

Size

32 bits

ADD-ON OUTGOING MAILBOX REGISTERS (AOMBX)

Add-On Outgoing Mailboxes

1-4

These four DWORD registers provide a method for sending

data, commands, or command parameters or status to the

PCI interface. Add-On write operations to these registers

may be in any width (byte, word, or DWORD). These regis-

ters may also be read. Writing to one of these registers can

optionally cause a PCI bus interrupt (if desired) when the

PCI interrupt control/status register is properly configured.

Mailbox 4, byte 3 only exists as device pins on the S5935

device when used with a serial nonvolatile memory. This

byte is not available if a byte-wide nv memory is used.

Add-On Address Offset

10h, 14h, 18h, 1Ch

Power-up value

XXXXXXXXh

Attribute

Read/Write

Size

32 bits

ADD-ON FIFO REGISTER PORT (AFIFO)

Add-On FIFO Port

This location provides access to the bidirectional FIFO. Separate registers are

involved when reading and writing to this location. Accordingly, it is not possible

to read what was written to this location. The sequence of filling and emptying

this FIFO is established by the PCI interface interrupt control and Status Regis-

ter.

The FIFO’s fullness may be observed by reading the master control/status regis-

ter or AGCSTS register Additionally, two signal pins are provided which reveal

whether data is available (RDEMPTY) or space to write into the FIFO is available

(WRFULL). These signals may be used to interface with user supplied DMA

logic. Caution must be exercised when using these flags for FIFO transfers

involving 64 bit endian conversion since the FIFO must operate on DWORD

pairs.

Add-On Address

Offset

20h

Power-up value

XXXXXXXXh

Attribute

Read/Write

Size

32 bits

S5935 Datasheet(PDF) 77 Page - Applied Micro Circuits Corporation

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