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S5935 Datasheet(PDF) 83 Page - Applied Micro Circuits Corporation |
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S5935 Datasheet(HTML) 83 Page - Applied Micro Circuits Corporation |
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83 / 204 page ![]() S5935 – PCI Product Revision 1.02 – June 27, 2006 AMCC Confidential and Proprietary DS1527 83 Data Book ADD-ON INTERRUPT CONTROL/STATUS REGISTER (AINT) This register provides the method for choosing which conditions are to produce an interrupt on the Add-On bus interface, a method for viewing the cause for the interrupt, and a method for acknowledging (removing) the interrupt’s assertion. Interrupt sources: • One of the Incoming mailboxes (1,2,3 or 4) becomes full. • One of the Outgoing mailboxes (1,2,3 or 4) becomes empty. • Built-in self test issued. • Write Transfer Count = zero • Read Transfer Count = zero • Target/Master Abort Figure 35. Add-On Interrupt Control/Status Register Register Name Add-On Interrupt Control and Status Add-On Address Offset 38h Power-up value 00000000h Attribute Read/Write, Read/Write_One_Clear Size 32 bits 31 24 23 201918 21 17 12 8 4 0 Bit Value D4-D0 Incoming Mailbox (Becomes Full) D4=Enable Interrrupt D3-D2=Mailbox # 0 0=Mailbox 1 0 1=Mailbox 2 1 0=Mailbox 3 1 1=Mailbox 4 D0-D1=Byte # 0 0=Byte 0 0 1=Byte 1 1 0=Byte 2 1 1=Byte 3 D12-D8 Outgoing Mailbox (R/W) (Goes empty) D12=Enable Interrupt D11-D10=Mailbox 0 0=Mailbox 1 0 1=Mailbox 2 1 0=Mailbox 3 1 1=Mailbox 4 D9-D8=Byte # 0 0=Byte 0 0 1=Byte 1 1 0=Byte 2 1 1=Byte 3 16 1514 0 0 0 0 0 0 0 0 0 0 Interrupt Asserted (RO) Bus Mastering Error Interrupt (R/WC) BIST (R/WC) Read Transfer Complete (R/WC) Write Transfer Complete (R/WC) Interrupt on Read Transfer Complete Outgoing Mailbox Interrupt (R/WC) Incoming Mailbox Interrupt (R/WC) 0 0 0 Interrupt Source (R/W) Enable & Selection Interrupt on Write Transfer Complete Interrupt Status Interrupt Selection |
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