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PCAL6408A

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Product data sheet

Rev. 3 — 18 September 2013

25 of 49

NXP Semiconductors

PCAL6408A

Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander

IOL

LOW-level output current

VOL =0.4 V; VDD(P) =1.65V to 5.5V

[4]

SDA

INT

315[5]

-mA

input current

VDD(P) = 1.65 V to 5.5 V

SCL, SDA, RESET; VI =VDD(I2C-bus) or VSS

1

A

ADDR; VI =VDD(P) or VSS

1

A

IIH

HIGH-level input current

P port; VI =VDD(P); VDD(P) =1.65V to 5.5V

A

IIL

LOW-level input current

P port; VI =VSS; VDD(P) = 1.65 V to 5.5 V

A

IDD

supply current

IDD(I2C-bus) +IDD(P); Operating mode;

SDA, P port, ADDR, RESET;

VI on SDA and RESET =VDD(I2C-bus) or VSS;

VI on P port and ADDR = VDD(P) or VSS;

IO = 0 mA; I/O = inputs; fSCL = 400 kHz

VDD(P) = 3.6 V to 5.5 V

A

VDD(P) = 2.3 V to 3.6 V

6.5

A

VDD(P) = 1.65 V to 2.3 V

A

IDD(I2C-bus) +IDD(P); Standby mode;

SCL, SDA, P port, ADDR, RESET;

VI on SCL, SDA and RESET =VDD(I2C-bus) or VSS;

VI on P port and ADDR = VDD(P);

IO = 0 mA; I/O = inputs; fSCL = 0 kHz

VDD(P) = 3.6 V to 5.5 V

1.5

A

VDD(P) = 2.3 V to 3.6 V

3.2

A

VDD(P) = 1.65 V to 2.3 V

0.5

1.7

A

Active mode; IDD(I2C-bus) +IDD(P);

P port, ADDR, RESET;

VI on RESET =VDD(I2C-bus);

VI on P port and ADDR = VDD(P);

IO = 0 mA; I/O = inputs;

fSCL = 400 kHz, continuous register read

VDD(P) = 3.6 V to 5.5 V

125

A

VDD(P) = 2.3 V to 3.6 V

A

VDD(P) = 1.65 V to 2.3 V

A

with pull-ups enabled;

IDD(I2C-bus) +IDD(P); P port, ADDR, RESET;

VI on SCL, SDA and RESET =VDD(I2C-bus) or VSS;

VI on P port = VSS;

VI on ADDR = VDD(I2C-bus) or VSS;

IO = 0 mA; I/O = inputs with pull-up enabled;

fSCL = 0 kHz

VDD(P) = 1.65 V to 5.5 V

0.55

0.75

Table 23.

Static characteristics …continued

Tamb = 40 C to +85 C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ[1] Max

Unit

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