PCAL6408A

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© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 3 — 18 September 2013

26 of 49

NXP Semiconductors

PCAL6408A

Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander

[1]

All typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V or 5 V VDD) and Tamb =25 C.

[2]

When power (from 0 V) is applied to VDD(P), an internal power-on reset holds the PCAL6408A in a reset condition until VDD(P) has

reached VPOR. At that time, the reset condition is released, and the PCAL6408A registers and I2C-bus/SMBus state machine initialize to

their default states. After that, VDD(P) must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle.

[3]

The total current sourced by all I/Os must be limited to 80 mA.

[4]

Each I/O must be externally limited to a maximum of 25 mA, for a device total of 200 mA.

[5]

Typical value for Tamb =25 C. VOL = 0.4 V and VDD = 3.3 V. Typical value for VDD <2.5 V, VOL =0.6 V.

[6]

Internal pull-up/pull-down resistor disabled.

I

DD

additional quiescent

supply current[6]

SCL, SDA, RESET;

one input at VDD(I2C-bus)  0.6 V,

other inputs at VDD(I2C-bus) or VSS;

VDD(P) = 1.65 V to 5.5 V

--

25

A

P port, ADDR;

one input at VDD(P)  0.6 V,

other inputs at VDD(P) or VSS;

VDD(P) = 1.65 V to 5.5 V

--

80

A

Ci

input capacitance

SCL; VI =VDD(I2C-bus) or VSS;

VDD(P) = 1.65 V to 5.5 V

-6

7

pF

Cio

input/output capacitance

SDA; VI/O =VDD(I2C-bus) or VSS;

VDD(P) = 1.65 V to 5.5 V

-7

8

pF

P port; VI/O =VDD(P) or VSS;

VDD(P) = 1.65 V to 5.5 V

-7.5

8.5

pF

Rpu(int)

internal pull-up resistance input/output

50

100

150

k



Rpd(int)

internal pull-down

resistance

input/output

50

100

150

k



Table 23.

Static characteristics …continued

Tamb = 40 C to +85 C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ[1] Max

Unit