[AK4344]

SWITCHING CHARACTERISTICS

(Ta=25

Parameter

Symbol

min

typ

max

Units

Master Clock Frequency

Half Speed Mode (512/768/1024/1536fs)

Normal Speed Mode (256/384/512/768fs)

Double Speed Mode (128/192/256/384fs)

Duty Cycle

fCLK

fCLK

fCLK

dCLK

4.096

2.048

6.144

40

36.864

36.864

36.864

60

MHz

MHz

MHz

%

LRCK Frequency

Half Speed Mode

(DFS1-0 = “10”)

Normal Speed Mode (DFS1-0 = “00”)

Double Speed Mode

(DFS1-0 = “01”)

Duty Cycle

fsh

fsn

fsd

dCLK

8

8

48

45

24

48

96

55

kHz

kHz

kHz

%

Audio Interface Timing

BICK Period

Half Speed Mode

Normal Speed Mode

Double Speed Mode

BICK Pulse Width Low

Pulse Width High

BICK “

↑” to LRCK Edge

(Note 11)

LRCK Edge to BICK “

↑”

(Note 11)

SDTI Hold Time

SDTI Setup Time

tBCK

tBCK

tBCK

tBCKL

tBCKH

tBLR

tLRB

tSDH

tSDS

1/128fs

1/128fs

1/64fs

70

70

40

40

40

40

ns

ns

ns

ns

ns

ns

ns

ns

ns

Control Interface Timing

CCLK Period

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN “H” Time

CSN “

↓” to CCLK “↑”

CCLK “

↑” to CSN “↑”

CDTO Delay

CSN “

↑” to CDTO Hi-Z

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

tDCD

tCCZ

200

80

80

40

40

150

150

50

45

70

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Power-Down & Reset Timing

PDN Pulse Width

(Note 12)

tPD

4

ms/μF

Note 11. BICK rising edge must not occur at the same time as LRCK edge.

Note 12. The AK4344 can be reset by bringing PDN pin = “L”.

The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4000

× C.

When C = 4.7

μF, tPD is 19ms(min).

The value of the capacitor (C) connected with VCOM pin should be 1

μF ≤ C ≤ 10μF.

When the states of DIF1-0 pins change, the AK4344 should be reset by PDN pin.

MS0641-E-00

2007/06

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