[AK4344]

OPERATION OVERVIEW

The external clocks, which are required to operate the AK4344, are MCLK, BICK and LRCK. The master clock (MCLK)

should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation

filter and the delta-sigma modulator. The MCLK frequency is detected from the relation between MCLK and LRCK

automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0 bits (Table 1).

The sampling speed mode is set depending on the MCLK frequency automatically for Auto mode (DFS1 bit = DFS0 bit =

“1”) (Table 2).

The AK4344 is automatically placed in the reset mode when MCLK stops in the normal operation mode (PDN pin = “H”),

and the analog output becomes the VCOM voltage. After MCLK is input again, the AK4344 is powered up. After exiting

reset by PDN pin at power-up etc., the AK4344 is in the reset mode until MCLK and LRCK are input.

Mode

DFS1

DFS0

fs

MCLK Frequency

Normal Speed

0

0

8

∼ 48kHz

256/384/512/768fs

Double Speed

0

1

48

∼ 96kHz

128/192/256/384fs

Half Speed

1

0

8

∼ 24kHz

512/768/1024/1536fs

Auto

1

1

8

∼ 96kHz

Table 2

Table 1. System Clock Example

MCLK Frequency

Sampling Speed Mode

Fs

512/768fs

Normal Speed

8

∼ 48kHz

128/192/256/384fs

Double Speed

48

∼ 96kHz

1024/1536fs

Half Speed

8

∼ 24kHz

Table 2. Auto Mode

The Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 bits as shown in Table 3 can select four

serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of

≥ 48fs or BICK = 32fs.

Mode

DIF1

DIF0

SDTI Format

BICK

Figure

0

0

0

16bit, LSB justified

≥ 32fs

Figure 10

1

0

1

24bit, LSB justified

≥ 48fs

Figure 11

2

1

0

24bit, MSB justified

≥ 48fs

Figure 12

3

1

1

Figure 13

≥ 48fs or 32fs

Table 3. Audio Interface Format

MS0641-E-00

2007/06

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