ADS5232 datasheet(18/29 Pages) TI

18 / 29 page

www.ti.com

APPLICATION INFORMATION

THEORY OF OPERATION

INPUT CONFIGURATION

INPUT DRIVER CONFIGURATIONS

Transformer-Coupled Interface

ADS5232

SBAS294A – JUNE 2004 – REVISED MARCH 2006

The

ADS5232

dual-channel,

simultaneous

The analog input for the ADS5232 consists of a

sampling analog-to-digital converter (ADC). Its low

differential sample-and-hold architecture implemented

power and high sampling rate of 65MSPS is achieved

using a switched capacitor technique; see Figure 18.

using a state-of-the-art switched capacitor pipeline

The sampling circuit consists of a low-pass RC filter

architecture built on an advanced low-voltage CMOS

at the input to filter out noise components that

process. The ADS5232 operates from a +3.3V supply

potentially could be differentially coupled on the input

voltage for both

its

analog

and

digital

supply

pins. The inputs are sampled on two 4pF capacitors.

connections. The ADC core of each channel consists

The RLC model is illustrated in Figure 18.

of a combination of multi-bit and single-bit internal

pipeline stages. Each stage feeds its data into the

digital

error

correction

logic,

ensuring

excellent

differential linearity and no missing codes at the

12-bit level. The conversion process is initiated by the

If the application requires a signal conversion from a

rising edge of the external clock. Once the signal is

single-ended

source

drive

the

ADS5232

captured by the input sample-and-hold amplifier, the

differentially, an RF transformer could be a good

input sample is sequentially converted within the

solution. The selected transformer must have a

pipeline stages. This process results in a data latency

center tap in order to apply the common-mode DC

of six clock cycles, after which the output data is

voltage (VCM) necessary to bias the converter inputs.

available as a 12-bit parallel word, coded in either

AC grounding the center tap will generate the

straight

offset

binary

(SOB)

binary

two's

differential

signal

swing

across

the

secondary

complement (BTC) format. Since a common clock

winding. Consider a step-up transformer to take

controls the timing of both channels, the analog

advantage

signal

amplification

without

the

signal is sampled simultaneously. The data on the

introduction of another noise source. Furthermore,

parallel ports is updated simultaneously as well.

the reduced signal swing from the source may lead to

Further processing can be timed using the individual

improved distortion performance. The differential

data valid output signal of each channel. The

input

configuration

may

provide

noticeable

ADS5232

features

internal

references

that

are

advantage for achieving good SFDR performance

trimmed to ensure a high level of accuracy and

over a wide range of input frequencies. In this mode,

matching. The internal references can be disabled to

both inputs (IN and IN) of the ADS5232 see matched

allow for external reference operation.

impedances.

Figure 19 illustrates the schematic for the suggested

transformer-coupled interface circuit. The component

values of the RC low-pass filter may be optimized

depending on the desired roll-off frequency.

Submit Documentation Feedback

ADS5232 Datasheet(PDF) 18 Page - Texas Instruments

ADS5232 Datasheet(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL