ADS5232 datasheet(24/29 Pages) TI

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LAYOUT AND DECOUPLING

ADS5232

SBAS294A – JUNE 2004 – REVISED MARCH 2006

output buffer supply pins, VDRV. In order to minimize

CONSIDERATIONS

the lead and trace inductance, the capacitors should

be located as close to the supply pins as possible.

Proper grounding and bypassing, short lead length,

Where double-sided component mounting is allowed,

and the use of ground planes are particularly

they are best placed directly under the package. In

important for high frequency designs. Achieving

addition, larger bipolar decoupling capacitors (2.2

µF

optimum performance with a fast sampling converter

to 10

µF), effective at lower frequencies, may also be

such as the ADS5232 requires careful attention to the

used on the main supply pins. They can be placed on

printed circuit board (PCB) layout to minimize the

the PCB in proximity (< 0.5") to the ADC.

effects of board parasitics and to optimize component

placement. A multilayer board usually ensures best

If the analog inputs to the ADS5232 are driven

results and allows convenient component placement.

differentially, it is especially important to optimize

towards a highly symmetrical layout. Small trace

The ADS5232 should be treated as an analog

length

differences

may

create

phase

shifts,

component and the supply pins connected to clean

compromising a good distortion performance. For this

analog supplies. This layout ensures the most

reason, the use of two single op amps rather than

consistent performance results, since digital supplies

one dual amplifier enables a more symmetrical layout

often carry a high level of switching noise, which

and a better match of parasitic capacitances. The pin

could couple into the converter and degrade device

orientation of the ADS5232 quad-flat package follows

performance. As mentioned previously, the output

a flow-through design, with the analog inputs located

buffer supply pins (VDRV) should also be connected

on one side of the package while the digital outputs

to a low-noise supply. Supplies of adjacent digital

are located on the opposite side. This design

circuits may carry substantial current transients. The

provides a good physical isolation between the

supply voltage should be filtered before connecting to

analog and digital connections. While designing the

the VDRV pin of the converter. All ground pins should

layout, it is important to keep the analog signal traces

directly connect to an analog ground.

separated from any digital lines to prevent noise

coupling onto the analog portion.

Because

its

high

sampling

frequency,

the

ADS5232 generates high frequency current transients

Single-ended clock lines must be short and should

and noise (clock feed-through) that are fed back into

not cross any other signal traces.

the supply and reference lines. If not sufficiently

bypassed, this feed-through adds noise to the

Short circuit traces on the digital outputs will minimize

conversion process. All AVDD pins may be bypassed

capacitive loading. Trace length should be kept short

with 0.1

µF ceramic chip capacitors (size 0603, or

to the receiving gate (< 2") with only one CMOS gate

smaller). A similar approach may be used on the

connected to one digital output.

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