ML145502, ML145503, ML145505

LANSDALE Semiconductor, Inc.

Figure 1. Test Circuit

* To define RDD when TDD is high Z.

ML145503

VAG

RxO

+ Tx

TxI

– Tx

Mu/A

PDI

VSS

VDD

RDD

RCE

RDC

TDC

TDD

TDE

VLS

1

2

3

4

5

6

7

89

10

11

12

13

14

16

15

600

Ω

5 k

Ω

10 k

Ω

681

VAG

Rx

Tx

– 5 V

CLOCK

ENABLE

51 k

Ω*

5 V

0.1

µF

0.1

µF

Table 1. Options Available by Pin Selection

RSI*

Pin Level

Vref*

Pin Level

Peak–to–Peak Overload Voltage

(Txl, RxO)

VDD

VSS

7.56 V p–p

VDD

VAG + VEXT

(3.02 x VEXT) V p–p

VAG

VSS

5 V p–p

VAG

VAG + VEXT

(2 x VEXT) V p–p

VSS

VSS

6.3 V p–p

VSS

VAG + VEXT

(2.52 x VEXT) V p–p

* On ML145503/05, RSI and Vref tied internally to VSS .

Table 2. Summary of Operation Conditions User Programmed Through Pins VDD, VAG, and VSS

Pin

Programmed

Logic

Level

Mu/A

RSI

Peak Overload

Voltage

VLS

VDD

Mu–Law Companding Curve and D3/D4 Digital

Formats with Zero Code Suppress

3.78

CMOS

Logic Levels

VAG

Mu–Law Companding Curve and Sign

Magnitude Data Format

2.50

TTL Levels

VAG Up

VSS

A–Law Companding Curve and CCITT Digital

Format

3.15

TTL Levels

VSS Up

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Issue A