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SN8F27E64LKB Datasheet(PDF) 25 Page - SONiX Technology Company |
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SN8F27E64LKB Datasheet(HTML) 25 Page - SONiX Technology Company |
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25 / 192 page ![]() SN8F27E60 Series 8-Bit Flash Micro-Controller with Embedded ICE and ISP SONiX TECHNOLOGY CO., LTD Page 25 Version 1.4 2.2 DATA MEMORY (RAM) 512 X 8-bit RAM Bank Address RAM Location Comment Bank 0 000H General purpose area RAM Bank 0 ... ... 07FH 080H System Register ... 0FFH End of Bank 0 Bank 1 100H General purpose area RAM Bank 1 … … 1FFH End of Bank 1 Bank 2 200H General purpose area RAM Bank 2 … … 27FH End of Bank 2 The 512-byte general purpose RAM is separated into Bank0, Bank1 and Bank2. Accessing the three banks ’ RAM is controlled by “RBANK” register. When RBANK = 0, the program controls Bank 0 RAM directly. When RBANK = 1, the program controls Bank 1 RAM directly. When RBANK = 2, the program controls Bank 2 RAM directly. Under one bank condition and need to access the other bank RAM, setup the RBANK register is necessary. When interrupt occurs, RBANK register is saved, and RAM bank is still last condition. User can select RAM bank through setup RBANK register during processing interrupt service routine. When RETI is executed to leave interrupt operation, RBANK register is reloaded, and RAN bank returns to last condition. Sonix provides “Bank 0” type instructions (e.g. b0mov, b0add, b0bts1, b0bset …) to control Bank 0 RAM in non-zero RAM bank condition directly. Example: Access Bank 0 RAM in Bank 1 condition. Move Bank 0 RAM (WK00) value to Bank 1 RAM (WK01). ; Bank 1 (RBANK = 1) B0MOV A, WK00 ; Use Bank 0 type instruction to access Bank 0 RAM. MOV WK01,A Note: 1. For multi-bank RAM program, it is not easy to control RAM Bank selection. Users have to take care the RBANK condition very carefully, especially for interrupt service routine. The system won’t save the RBANK and switch RAM bank to Bank 0, so these controls must be through program. It is a good to use Bank 0 type instruction to process the situations. 2. The 190H, 191H of RAM address doesn ’t support directly addressing mode to access RAM but support indirectly addressing mode @HL/@YZ. |
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