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EM78P808 Datasheet(PDF) 52 Page - ELAN Microelectronics Corp |
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EM78P808 Datasheet(HTML) 52 Page - ELAN Microelectronics Corp |
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52 / 63 page  EM78808 8-bit Micro-controller ______________________________________________________________________________________________________________________________________________________ * This specification is subject to change without notice. 52 8/1/2004 (V3.1) Tone1/Tone2 signal strength (root mean square voltage) Tone1 signal strength V1rms (ps1) 130 155 180 ｍV Tone2 signal strength V2rms (ps1) 1.259V1rms ｍV Tone twist (Tone1 – Tone2) twist -2 dB Tone frequency deviation Frequency deviation ±1 % (ps1) : V1rms and V2rms has 2 dB difference. It means 20log(V2rms/V1rms) = 20log1.259 = 2 (dB) (DED AC Characteristic)(Vdd=+5.0V,Ta=+25℃) CHARACTERISTIC MIN TYP MAX UNIT Input sensitivity TIP and RING for DED, DEDTHD bit=0 -45 -- dBm Input sensitivity TIP and RING for DED, DEDTHD bit=1 -35 -- dBm Timing characteristic (Vdd=5V,Ta=+25 °C) Description Symbol Min Typ Max Unit Oscillator timing characteristic OSC start up 32.768kHz Tosc 400 ms 3.579MHz PLL 10 FSK timing characteristic Carrier detect low Tcdl -- 10 14 ms Data out to Carrier det low Tdoc -- 10 20 ns Power up to FSK(setup time) Tsup -- 15 20 ms End of FSK to Carrier Detect high Tcdh -- 4 ms CW timing characteristic CAS input signal length (2130 ,2750 Hz @ -20dBm ) Tcasi 80 ms Call waiting data detect delay time Tcwd 42 ms Call waiting data release time Tcwr 26 ms DTMF receiver timing characteristic Tone Present Detection Time Tdp (ps1) the guard-times for tone-present (C=0.1uF, R=300K) Tgtp 30 ms the guard-times for tone-absent (C=0.1uF, R=300K) Tgta 30 mS Propagation Delay (St to Q) Tpq 8 us Tone Absent Detection Time Tda (ps2) ms SPI timing characteristic (CPU clock 3.58MHz and Fsco = 3.58Mhz /2) /SS set-up time Tcss 560 ns /SS hold time Tcsh 250 SCLK high time Thi 250 ns SCLK low time Tlo 250 ns SCLK rising time Tr 15 30 ns SCLK falling time Tf 15 30 ns SDI set-up time to the reading edge of SCLK Tisu 25 ns SDI hold time to the reading edge of SCLK Tihd 25 ns SDO disable time Tdis 560 ns (ps1) : Controlled by software (ps2) : Controlled by RC circuit. |
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