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PT4316 V1.6

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August, 2007

Low Power 315/433 MHz OOK/ASK Superheterodyne

Receiver with SAW-based Oscillator

PT4316

PEAK DETECTOR

The peak detector generates a DC voltage which is proportional to the peak value of the received data

signal. An external R-C network is necessary. The peak detector input is connected to the RSSI output

of the limiter and the output is connected to pin 8 (DSP). This output can be used as an indicator for the

received signal strength for use in wake-up circuits and as a reference for the data slicer in ASK mode.

The time constant is calculated with the driving current of the data filter op-amp, 100

µA. Circuit for

using peak detector for faster start-up as the following figure.

Data Output

Data Slicer

R4

Data Filter

C12

12

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R5

DATA SLICER

The data slicer consists chiefly of a fast comparator, which allows for a maximum receive data rate of

up to 50Kb/s. The maximum achievable data rate also depends upon the IF filter bandwidth. Both data

slicer inputs are accessible off-chip to allow for easy adjustment of the slicing threshold. The output

delivers a digital data signal (CMOS level) for subsequent circuits. The self-adjusting threshold on pin

12(DSN) is generated by an R-C network or peak detector depending upon the baseband coding

scheme.

The suggested data slicer configuration uses an internal 100K

Ω resistor connected between DSN and

DSP with a capacitor from DSN to ground as shown in the following figure. The cut-off frequency of the

R-C integrator must be set lower than the lowest frequency appearing in the data signal to minimize

distortion in the output signal. Circuit for generating data slicer threshold as following figure.

Data Output

Data Slicer

Data Filter

C12

12

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