Data Sheet

AD3530/AD3530R

REGISTER DETAILS

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Rev. 0 | 35 of 45

Table 23. Bit Descriptions for TRANSFER_CONFIG (Continued)

Bits

Bit Name

Description

Reset

Access

[1:0]

RESERVED

Reserved.

0x0

R

INTERFACE CONFIGURATION C REGISTER

Address: 0x10, Reset: 0x23, Name: INTERFACE_CONFIG_C

Additional Interface Configuration Settings

0

1

1

1

2

0

3

0

4

0

5

1

6

0

7

0

[7:6] CRC_ENABLE (R/W)

[1:0] CRC_ENABLEB (R/W)

[5] STRICT_REGISTER_ACCESS (R)

[3:2] ACTIVE_INTERFACE_MODE (R)

[4] RESERVED

Table 24. Bit Descriptions for INTERFACE_CONFIG_C

Bits

Bit Name

Description

Reset

Access

[7:6]

CRC_ENABLE

CRC Enable. This register is written to enable/disable the use of CRC on the interface. The

CRC_EnableB bit field must also be written with the inverted value of this bit field for the CRC to

be enabled.

0x0

R/W

00: CRC disabled.

01: CRC enabled.

5

STRICT_REGISTER_ACCESS

Multibyte Registers Must Be Read/Written in Full. When this mode is enabled, all bytes of a

multibyte register must be read/written in full.

0x1

R

0: Normal mode; no access restrictions.

1: Strict mode; multibyte registers require all bytes accessed.

4

RESERVED

Reserved.

0x0

R

[3:2]

ACTIVE_INTERFACE_MODE

Active Mode the SPI Interface Is Operating In.

0x0

R

[1:0]

CRC_ENABLEB

Inverted CRC Enable. This must be written with the inverted value of the CRC_ENABLE.

10: CRC enabled.

11: CRC disabled.

0x3

R/W

INTERFACE STATUS A REGISTER

Address: 0x11, Reset: 0x00, Name: INTERFACE_STATUS_A

Status bits are set to 1 to indicate an active condition. They may be cleared by writing a 1 to the corresponding bit location.

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

[7] NOT_READY_ERR (R/W1C)

[0] RESERVED

[6:5] RESERVED

[1] REGISTER_PARTIAL_ACCESS_ERR (R/W1C)

[4] CLOCK_COUNT_ERR (R/W)

[2] RESERVED

[3] CRC_ERR (R/W1C)

Table 25. Bit Descriptions for INTERFACE_STATUS_A

Bits

Bit Name

Description

Reset

Access

7

NOT_READY_ERR

Device Not Ready for Transaction. This error bit is set if the user attempts to execute a SPI

transaction before the completion of digital initialization.

0x0

R/W1C

[6:5]

RESERVED

Reserved.

0x0

R

4

CLOCK_COUNT_ERR

Incorrect Number of Clocks Detected in a Transaction.

0x0

R/W

3

CRC_ERR

Invalid/No CRC Received. This is set when the controller fails to send a CRC or when the

device calculates and checks the CRC and finds the CRC value is incorrect.

0x0

R/W1C

2

RESERVED

Reserved.

0x0

R