Data Sheet

AD3530/AD3530R

REGISTER DETAILS

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Rev. 0 | 44 of 45

Table 39. Bit Descriptions for MULTI_INPUT_SEL_0 (Continued)

Bits

Bit Name

Description

Reset

Access

0: MI Sel 0. Deselect INPUT_CH3 for MULTI_INPUT_CH operation.

1: MI Sel 1. Select INPUT_CH3 for MULTI_INPUT_CH operation.

2

MI_SEL_CH_2

Multiple Input Select Channel 2. If selected, write operation on MULTI_INPUT_CH also writes INPUT_CH2 with

the same data. If deselected, write operation on Multi_DAC_Ch will have no effect on INPUT_CH2.

0x1

R/W

0: MI Sel 0. Deselect INPUT_CH2 for MULTI_INPUT_CH operation.

1: MI Sel 1. Select INPUT_CH2 for MULTI_INPUT_CH operation.

1

MI_SEL_CH_1

Multiple Input Select Channel 1. If selected, write operation on MULTI_INPUT_CH also writes INPUT_CH1 with

the same data. If deselected, write operation on Multi_DAC_Ch will have no effect on INPUT_CH1.

0x1

R/W

0: MI Sel 0. Deselect INPUT_CH1 for MULTI_INPUT_CH operation.

1: MI Sel 1. Select INPUT_CH1 for MULTI_INPUT_CH operation.

0

MI_SEL_CH_0

Multiple Input Select Channel 0. If selected, write operation on MULTI_INPUT_CH also writes INPUT_CH0 with

the same data. If deselected, write operation on Multi_DAC_Ch will have no effect on INPUT_CH0.

0x1

R/W

0: MI Sel 0. Deselect INPUT_CH0 for MULTI_INPUT_CH operation.

1: MI Sel 1. Select INPUT_CH0 for MULTI_INPUT_CH operation.

SOFTWARE LDAC TRIGGER 0 REGISTER

Address: 0xE9, Reset: 0x00, Name: SW_LDAC_TRIG_0

Initiates transfer of INPUT_CHn to DAC_CHn; only takes effect on enabled channels identified by SW_LDAC_EN_0

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

[7] SLD_TRIG_0 (W)

[6:0] RESERVED

Table 40. Bit Descriptions for SW_LDAC_TRIG_0

Bits

Bit Name

Description

Reset

Access

7

SLD_TRIG_0

Software LDAC Trigger 0. When set, initiates transfer of INPUT_CHn to DAC_CHn, where n is the channel number

as enabled by SW_LDAC_EN_0. Writing 0 has no effect.

0x0

W

[6:0]

RESERVED

Reserved.

0x0

R

INPUT REGISTER

Address: 0xEA to 0xF8 (increments of 2), Reset: 0x0000, Name: INPUT_CHn

A write to this register does not update the output voltage of the device; hardware LDAC or software LDAC is required to push data from

INPUT_CHn to DAC_CHn, which also updates the output

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

8

0

9

0

10

0

11

0

12

0

13

0

14

0

15

0

[15:0] INPUT_VAL (R/W)

Table 41. Bit Descriptions for INPUT_CHn

Bits

Bit Name

Description

Reset

Access

[15:0]

INPUT_VAL

Input Value. 16-bit INPUT_CHn data where n is the channel number.

0x0

R/W