AD3530 datasheet(25/45 Pages) AD

25 / 45 page

Data Sheet

AD3530/AD3530R

APPLICATIONS INFORMATION

analog.com

Rev. 0 | 25 of 45

POWER SUPPLY RECOMMENDATIONS

The AD3530/AD3530R do not have any restrictions for power

supply sequencing. The outputs are maintained at POR state with a

known pull-down resistance until proper register configurations are

set.

The AD3530/AD3530R must have an ample supply bypassing of

10μF in parallel with 0.1μF on each supply, located as close to

the package as possible (ideally directly against the device). The

VREF pin, on the other hand, has a maximum capacitive load of

0.5nF as stated in Table 2. The 10μF capacitors are the tantalum

bead type. The 0.1μF and 0.5nF capacitors must have low effective

series resistance (ESR) and low effective series inductance (ESL).

Common ceramic capacitors provide a low impedance path to

ground at high frequencies to handle transient currents due to

internal logic switching.

LAYOUT GUIDELINES

The pin configurations of the AD3530/AD3530R are arranged in a

way that facilitates optimal layout, an example of which is shown

in Figure 69. Most digital high speed lines are located on one side

of the chip, with the analog functions of each DAC symmetrically

distributed along the other three sides. This arrangement allows

routing of the digital lines straight away from the analog functions.

Figure 69. Evaluation Board Layout

The following are some PCB design recommendation to obtain the

best performance for the AD3530/AD3530R:

►

Ensure that the power supply line has as large a trace as

possible to provide a low impedance path and reduce glitch

effects on the supply line.

►

A low impedance analog ground plane and star grounding tech-

niques are recommended. It is advised to keep the ground layer

continuous to minimize ground resistance.

►

Shield clocks and other fast switching digital signals from other

parts of the board by using a digital ground.

►

Avoid crossover of digital and analog signals if possible. When

traces cross on opposite sides of the board, ensure that they run

at 45° or 90° angles to each other to reduce feedthrough effects

through the board.

►

For clock rates around the device maximum of 50MHz, it is

advised to add series resistors near the source I/O pins. Values

from 22Ω to 100Ω are commonly used and would help improve

signal integrity by reducing ringing and reflections caused by the

fast signal transitions.

HEADROOM AND FOOTROOM

Headroom and footroom refers to the voltage difference between

the supply voltage and the intended output voltage of the DAC for

a specified output load current. If the supply voltage headroom or

footroom is insufficient, the pass element of the integrated output

amplifier of the DAC acts like a resistor instead of an ideal switch.

This causes the output voltage to drop as the load current increas-

es.

The AD3530/AD3530R have very low typical headroom require-

ments of 25mV/20mA and 50mV/20mA for footroom. The typical

performance is shown in Figure 20. The voltage drop is generally

linear in nature, hence, can be calculated by multiplying the load

current by the headroom/footroom specification. For example, we

have a 5V supply and a 5V setting at the output of the DAC. If

the DAC starts sourcing current of 30mA to a load, the DAC output

voltage would be around 4.963V.

For a footroom example, a DAC output that is sinking 30mA of

current would result to an output voltage that is 75mV above ground

potential.

DAC UPDATE

There are multiple ways of updating the DAC_CHn registers,

hence VOUTn, Figure 70 shows a flow chart of options to update

DAC_CHn registers considering several factors such as single vs.

multiple channel updates, similar vs. unique data, and the mode of

LDAC.

AD3530 Datasheet(PDF) 25 Page - Analog Devices

AD3530 Datasheet(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL