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LTC4292 Datasheet(PDF) 21 Page - Analog Devices

Part # LTC4292
Description  24-/48-Port IEEE 802.3bt PoE PSE Controller
PDF  39 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

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Data Sheet
LTC9101-2B/LTC9102
APPLICATIONS INFORMATION
analog.com
Rev. 0 | 21 of 39
New in 802.3bt
The 802.3bt specification introduces several new features:
►
Type 3 PSEs may be constructed as 2-pair or 4-pair devices.
Type 4 PSEs shall be constructed as 4-pair devices.
►
Type 3 and Type 4 PSEs may provide power over all four
pairs (both pairsets), depending on the PSE construction and
connected PD characteristics.
►
Type 3 and Type 4 PDs are required to be capable of receiving
power over all four pairs (both pairsets).
►
Type 3 and 4 PDs can be formed as either a single-signature PD
or dual-signature PD. A single-signature PD presents the same
valid signature resistor to both pairsets simultaneously (see
Figure 36). A dual-signature PD presents two fully independent
valid detection signatures, one to each pairset.
►
Type 3 single-signature PDs request exactly one of six possible
power levels: 3.84W, 6.49W, 13W, 25.5W, 40W, or 51W.
►
Type 3 dual-signature PDs request exactly one of four possible
power levels on each pairset: 3.84W, 6.49W, 13W, or 25.5W.
The total PD requested power is the sum of the requested power
on both pairsets.
►
Type 3 PD Classes overlap with Type 1 and 2 Classes in order to
provide additional Type 3 feature sets at lower power levels.
►
Type 4 single-signature PDs request exactly one of two possible
power levels: 62W or 71.3W.
►
Type 4 dual-signature PDs request exactly 35.6W on at least one
pairset and one of five possible power levels on the other pairset:
3.84W, 6.49W, 13W, 25.5W, or 35.6W. The total PD requested
power is the sum of the requested power on both pairsets.
►
Classification is extended to a possible maximum of five class
events. The additional events allow for unique identification of
existing and new PD Classes.
►
Type 3 and 4 PSEs issue a long first class event to advertise
Type 3 and 4 feature support to attached PDs.
►
Lower standby power is enabled by shortening the length of the
maintain power signature pulse (short MPS). The PD duty cycle
drops from ~23% to ~2%. A PD is allowed to present short MPS
if the PSE issues a long first class event.
►
Power management is augmented by Autoclass, an optional
feature for 802.3bt PSEs and PDs. In an Autoclass system the
maximum PD power is measured and reported to the PSE host,
enabling the PSE to reclaim output power not used by the PD
application and losses in the Ethernet cabling (Table 7). See the
Autoclass section and LTC9101-2B Software Interface guide for
details.
Table 7. IEEE-Specified Power Allocations, Single-Signature PD
PD
CLASS
PSE OUTPUT
POWER
ALLOCATED CABLING
LOSS
PD INPUT POWER
1
4W
0.16W
3.84W
2
6.7W
0.21W
6.49W
3
14W
1W
13W
4
30W
4.5W
25.5W
5
45W
5W
40W
6
60W
9W
51W
7
75W
13W
62W
8
90W
18.7W
71.3W
DEVICE CONFIGURATION
An LTC9101-2B can control between one and four LTC9102. Each
LTC9102 controls 12 power channels. Thus, each LTC9101-2B can
control up to 48 power channels.
As described later in the Bus Addressing section, each group of
four channels occupies a single I2C address.
Table 8. Device Configuration Options
CFG[1:0]
NUMBER OF PORTS
NUM 9102s
I2C ADDRs
I2C ADDRESS OFFSET
0
1
2
3
4
5
6
7
8
9
10
11
0 (00b)
12
1
3
✓
✓
✓
1 (01b)
24
2
6
✓
✓
✓
✓
✓
✓
2 (10b)
36
3
9
✓
✓
✓
✓
✓
✓
✓
✓
✓
3 (11b)
48
4
12
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓



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