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WM8580 Datasheet(PDF) 77 Page - Wolfson Microelectronics plc |
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WM8580 Datasheet(HTML) 77 Page - Wolfson Microelectronics plc |
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77 / 97 page ![]() Production Data WM8580 w PD Rev 4.3 August 2007 77 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4 PLLB 1 04h 8:0 PLLB_K[8:0] 100100001 R5 PLLB 2 05h 8:0 PLLB_K[17:9] 101111110 3:0 PLLB_K[21:18] 1101 Fractional (K) part of PLLB frequency ratio (R). Value K is one 22-digit binary number spread over registers R4, R5 and R6 as shown. Note: PLLB_K must be set to specific values when the S/PDIF receiver is used. Refer to S/PDIF Receive Mode Clocking section for details. R6 PLLB 3 06h 7:4 PLLB_N[3:0] 0111 Integer (N) part of PLLB frequency ratio (R). Use values in the range 5 ≤ PLLB_N ≤ 13 as close as possible to 8 Note: PLLB_N must be set to specific values when the S/PDIF receiver is used. Refer to S/PDIF Receive Mode Clocking section for details. 0 PRESCALE_B 0 PLL Pre-scale Divider Select 0 = Divide by 1 (PLL input clock = oscillator clock) 1 = Divide by 2 (PLL input clock = oscillator clock ÷ 2) Note: PRESCALE_A must be set to the same value as PRESCALE_B in PLL S/PDIF receiver mode. 1 POSTSCALE_B 0 PLL Post-scale Divider Select PLL S/PDIF Receiver Mode POSTSCALE_A is used to configure a 256fs or 128fs PLLACLK, POSTSCALE_B is not used. Refer to Table 45. PLL User Mode Used in conjunction with the FREQMODE_x bits. Refer to Table 44. 4:3 FREQMODE_B [1:0] 10 PLL Output Divider Select PLL S/PDIF Receiver Mode FREQMODE_A is automatically controlled. FREQMODE_B is not used. PLL User Mode Used in conjunction with the POSTSCALE_x bits. Refer to Table 44. 6:5 MCLKOUTSRC 00 MCLK pin output source 00 = Input – Source MCLK pin 01 = Output – Source PLLACLK 10 = Output – Source PLLBCLK 11 = Output – Source OSCCLK R7 PLLB 4 07h 8:7 CLKOUTSRC 11 CLKOUT pin source 00 = No Output (tristate) 01 = Output – Source PLLACLK 10 = Output – Source PLLBCLK 11 = Output – Source OSCCLK 1:0 DAC_CLKSEL 00 DAC clock source 00 = MCLK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin R8 CLKSEL 08h 3:2 ADC_CLKSEL 00 ADC clock source 00 = ADCMLCK pin 01 = PLLACLK 10 = PLLBCLK 11 = MCLK pin |
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