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WM8580 Datasheet(PDF) 23 Page - Wolfson Microelectronics plc

Part # WM8580
Description  Multichannel CODEC with S/PDIF Transceiver
PDF  97 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8580 Datasheet(HTML) 23 Page - Wolfson Microelectronics plc

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Production Data
WM8580
w
PD Rev 4.3 August 2007
23
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R9
PAIF 1
09h
5
PAIFRX
MS
0
PAIF Receiver Master/Slave Mode Select:
0 = Slave Mode
1 = Master Mode
R10
PAIF 2
0Ah
5
PAIFTX
MS
0
PAIF Transmitter Master/Slave Mode Select:
0 = Slave Mode
1 = Master Mode
R11
SAIF 1
0Bh
5
SAIFMS
0
SAIF Master/Slave Mode Select:
0 = Slave Mode
1 = Master Mode
Table 12 Master Mode Registers
The frequency of a master mode LRCLK is dependant on system clock and the RATE register
control bits. Table 13 shows the settings for common sample rates and system clock frequencies.
MCLK CLOCK FREQUENCY (MHZ)
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
SAMPLING RATE
(LRCLK)
RATE =000
RATE =001
RATE =010
RATE =011
RATE =100
RATE =101
RATE =110
32kHz
4.096
6.144
8.192
12.288
16.384
24.576
36.864
44.1kHz
5.6448
8.467
11.2896
16.9344
22.5792
33.8688
Unavailable
48kHz
6.144
9.216
12.288
18.432
24.576
36.864
Unavailable
88.2kHz
11.2896
16.9344
22.5792
33.8688
Unavailable Unavailable Unavailable
96kHz
12.288
18.432
24.576
36.864
Unavailable Unavailable Unavailable
176.4kHz
22.5792
33.8688
Unavailable
Unavailable Unavailable Unavailable Unavailable
192kHz
24.576
36.864
Unavailable
Unavailable Unavailable Unavailable Unavailable
Table 13 Master Mode MCLK / LRCLK Frequency Selection
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R9
PAIF 1
09h
2:0
PAIFRX_RATE
[2:0]
010
R10
PAIF 2
0Ah
2:0
PAIFTX_RATE
[2:0]
010
R11
SAIF 1
0Bh
2:0
SAIF_RATE
[2:0]
010
Master Mode MCLK/LRCLK
Ratio:
000 = 128fs
001 = 192fs
010 = 256fs
011 = 384fs
100 = 512fs
101 = 768fs
110 = 1152fs
Table 14 Master Mode RATE Registers
In master mode, the BCLKSEL register controls the number of BCLKs per LRCLK. If the
MCLK:LRCLK ratio is 128fs or 192fs and BCLKSEL = 10, BCLKSEL is overwritten to be 128
BCLKs/LRCLK. Also, if BCLKSEL = 00, and LRCLK is 192fs or 1152fs, the generated BCLK has a
mark-space ratio of 1:2.



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