All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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http://www.DigitalCoreDesign.com

http://www.dcd.pl

Floating-Point math coprocessor - IEEE-

754 standard single precision real, word

and short integers

FADD, FSUB- addition, subtraction

FMUL, FDIV- multiplication, division

FSQRT- square root

FUCOM- compare

FCHS - change sign

FABS - absolute value

FSIN, FCOS- sine, cosine

FTAN, FATAN- tangent, arcs tangent

CONFIGURATION

The following parameters of the DP8051XP

core can be easy adjusted to requirements of

dedicated application and technology. Configu-

ration of the core can be prepared by effortless

changing appropriate constants in package file.

There is no need to change any parts of the

code.

- synchronous

•

Internal Program Memory

type

- asynchronous

-

•

Internal Program ROM

Memory size

-

0 - 64kB

-

•

Internal Program RAM

Memory size

-

0 - 64kB

- true

•

Internal Program Memory

fixed size

- false

- used

•

Second Data Pointer

(DPTR1)

- unused

- used

- unused

- used

- unused

- used

- unused

-

subroutines

location

- used

- unused

- used

- unused

- used

- unused

- used

- unused

Besides mentioned above parameters all

available peripherals and external interrupts

can be excluded from the core by changing

appropriate constants in package file.

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench environment

Active-HDL automatic simulation macros

ModelSim automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

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Delivery the IP Core updates, minor and

major versions changes

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Delivery the documentation updates

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Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design

license allows using IP Core in

single FPGA bitstream and ASIC implementa-

tion. It also permits FPGA prototyping before

ASIC production.

Unlimited Designs

license allows using IP Core

in unlimited number of FPGA bitstreams and

ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time of use

limitations.

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Single Design license for

VHDL, Verilog source code called HDL Sour-

ce

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Unlimited Designs license for

HDL Source

Netlist

Upgrade from

Netlist to HDL Source

Single Design to Unlimited Designs