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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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DESIGN FEATURES

PROGRAM MEMORY:

The DP8051XP soft core is dedicated for

operation with Internal and External Pro-

gram Memory. Internal Program Memory

can be implemented as:

ROM located in address range between

0x0000

÷ (ROM

RAM located in address range between

External Program Memory can be im-

plemented as ROM or RAM located in ad-

INTERNAL DATA MEMORY:

The DP8051XP can address Internal

Data Memory of up to 256 bytes The Inter-

nal Data Memory can be implemented as

Single-Port synchronous RAM.

EXTERNAL DATA MEMORY:

The DP8051XP soft core can address up

to 16 MB of External Data Memory. Extra

DPX (Data Pointer eXtended) register is

used for segments swapping.

USER

Up to 60 External (user) Special Func-

tion Registers (ESFRs) may be added to

the DP8051XP design. ESFRs are memory

mapped into Direct Memory between ad-

dresses 0x80 and 0xFF in the same man-

ner as core SFRs and may occupy any ad-

dress that is not occupied by a core SFR.

WAIT STATES SUPPORT:

The DP8051XP soft core is dedicated for

operation with wide range of Program and

Data memories. Slow Program and Exter-

nal Data memory may assert a memory

Wait signal to hold up CPU activity.

SYMBOL

port0i(7:0)

port1i(7:0)

port2i(7:0)

port3i(7:0)

port0o(7:0)

port1o(7:0)

port2o(7:0)

port3o(7:0)

reset

clk

ramdatai(7:0)

sfrdatai(7:0)

prgromdata(7:0)

prgramdata(7:0)

prgaddr(15:0)

prgdatao(7:0)

prgramwr

sfraddr(7:0)

sfrdatao(7:0)

sfroe

sfrwe

rxd0o

txd0

rxd0i

rxd1i

t0

gate0

t1

gate1

t2

t2ex

int0

int1

int2

int3

int4

int5

int6

xaddr(23:0)

xdatao(7:0)

xdataz

xdatai(7:0)

ramaddr(7:0)

ramdatao(7:0)

ramwe

ramoe

xprgrd

xprgwr

xdatard

xdatawr

stop

pmm

iprgromsize(2:0)

iprgramsize(2:0)

capture0

capture1

capture2

capture3

rxd1o

txd1

coderun

debugacs

rsto

scli

sdai

ss

si

mi

scki

sclhs

sclo

sdao

sssso(7:0)

so

mo

scko

scken

soen

ready

sxdmadd(15:0)

sxdmdatao(7:0)

sxdmwe

sxdmoe

sxdmxdatai(7:0)