All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

UART0

– Universal Asynchronous Receiver &

Transmitter module is full duplex, meaning it

can transmit and receive concurrently. Includes

Serial Configuration register (SCON), serial

receiver and transmitter buffer (SBUF) regis-

ters. Its receiver is double-buffered, meaning it

can commence reception of a second byte

before a previously received byte has been

read from the receive register. Writing to

SBUF0 loads the transmit register, and reading

SBUF0 reads a physically separate receive

register. It works in 3 asynchronous and 1 syn-

chronous modes. UART0 can be synchronized

by Timer 1 or Timer 2.

UART1

– Universal Asynchronous Receiver &

Transmitter module is full duplex, meaning it

can transmit and receive concurrently. Includes

Serial Configuration register (SCON1), serial

receiver and transmitter buffer (SBUF1) regis-

ters. Its receiver is double-buffered, meaning it

can commence reception of a second byte

before a previously received byte has been

read from the receive register. Writing to

SBUF1 loads the transmit register, and reading

SBUF1 reads a physically separate receive

register. It works in 3 asynchronous and 1 syn-

chronous modes. UART1 is synchronized by

Timer 1.

Master I2C Unit

– I2C bus controller is a Mas-

ter module. The core incorporates all features

required by I2C specification. It supports both

7-bit and 10-bit addressing modes on the I2C

bus. It works as a master transmitter and re-

ceiver. It can be programmed to operate with

arbitration and clock synchronization to allow it

operates in multi-master systems. Built-in timer

allows operation from a wide range of the input

frequencies. The timer allows achieving any

non-standard clock frequency. The I2C control-

ler supports all transmission modes: Standard,

Fast and High Speed up to 3400 kbps.

Slave I2C Unit

– I2C bus controller is a Slave

module. The core incorporates all features

required by I2C specification. It works as a

slave transmitter/receiver depending on work-

ing mode determined by a master device. The

I2C controller supports all transmission modes:

Standard, Fast and High Speed up to 3400

kbs.

SPI Unit

– it’s a fully configurable master/slave

Serial Peripheral Interface, which allows user

to configure polarity and phase of serial clock

signal SCK. It allows the microcontroller to

communicate with serial peripheral devices. It

is also capable of interprocessor communica-

tions in a multi-master system. A serial clock

line (SCK) synchronizes shifting and sampling

of the information on the two independent se-

rial data lines. SPI data are simultaneously

transmitted and received. SPI system is flexi-

ble enough to interface directly with numerous

standard product peripherals from several

manufacturers. Data rates as high as CLK/4.

Clock control logic allows a selection of clock

polarity and a choice of two fundamentally dif-

ferent clocking protocols to accommodate most

available synchronous serial peripheral de-

vices. When the SPI is configured as a master,

software selects one of four different bit rates

for the serial clock. SPI automatically drives

slave select outputs SSO[7:0], and address

SPI slave device to exchange serially shifted

data. Error-detection logic is included to sup-

port interprocessor communications. A write-

collision detector indicates when an attempt is

made to write data to the serial shift register

while a transfer is in progress. A multiple-

master mode-fault detector automatically dis-

ables SPI output drivers if more than one SPI

devices simultaneously attempts to become

bus master.

PROGRAM CODE SPACE

IMPLEMENTATIO N

The figure below shows an example Pro-

gram Memory space implementation in sys-

tems with DP8051XP Microcontroller core. The

On-chip Program Memory located in address

space between 0kB and 1kB is typically used

for BOOT code with system initialization func-

tions. This part of the code is typically imple-

mented as ROM. The On-chip Program Mem-

ory located in address space between 60kB

and 64kB is typically used for timing critical

part of the code e.g. interrupt subroutines,

arithmetic functions etc. This part of the code is

typically implemented as RAM and can be

loaded by the BOOT code during initialization

phase from Off-chip memory or through RS232

interface from external device. From the two

mentioned above spaces program code is

executed without wait-states and can achieve

a top performance up to 200 million instruc-

tions per second (many instructions executed

in one clock cycle). The Off-chip Program

Memory located in address space between

1kB and 60kB is typically used for main code

and constants. This part of the code is usually

implemented as ROM, SRAM or FLASH de-