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LTC4292 Datasheet(PDF) 7 Page - Analog Devices |
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LTC4292 Datasheet(HTML) 7 Page - Analog Devices |
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7 / 22 page ![]() Data Sheet LTC9105 PIN CONFIGURATION AND FUNCTION analog.com Rev. A | 7 of 22 Figure 2. Pin Configuration Table 5. Pin Function Pin No. Mnemonic Description 1 VIN PD Interface Supply Voltage. Positive input voltage for IEEE state machine and PD input voltage are referenced to this pin. 2 RSIG External Signature Resistor Connection. Connect a 24.9kΩ resistor between RSIG and VIN. 4 RCLSA Class Select Input. Connect a resistor between RCLSA and RTN per Table 6. 5 RCLSB Class Select Input. Connect a resistor between RCLSB and RTN per Table 6. 6 AUX Auxiliary Power Supply Input Sensing. This pin senses the presence of another power supply input. The AUX pin status is reflected in the aux_status bit. The AUX pin threshold can be configured by the aux_thresh bit. See Dual-Input Prioritization for a description of AUX pin behavior with respect to port or auxiliary priority. 8 SNSN Current Sense Negative Input. System current is monitored using a 50mΩ sense resistor between SNSP and SNSN. See Sense Resistor for kelvin sense requirements. 9 SNSP Current Sense Positive Input. System current is monitored using a 50mΩ sense resistor between SNSP and SNSN. See Sense Resistor for kelvin sense requirements. 10 GATE External Hot Swap MOSFET Gate Control. Connect to gate of the external MOSFET. 11 SDAOUT Serial Data Output. Open Drain Data Output for the I2C Serial Interface Bus. The LTC9105 uses two pins to implement the bidirectional SDA function to simplify isolation of the I2C bus. To implement a standard bidirectional SDA pin, tie SDAOUT and SDAIN together. See I2C Interface for more information. 13 PWRGD Power Good Open Drain Output. During inrush this pin sinks 250μA (typ.) to prevent the power supply from starting up. Current draw begins when VIN-RTN exceeds the VON threshold and continues for tPWRGD (93.75ms typ.). The PWRGD pin is high impedance before and after inrush. 14 SCL Serial Clock Input. High impedance clock input for the I2C serial interface bus. Internally pulled up to BYP through a 50kΩ (typ.) resistor. See I2C Interface for more information. 15 SDAIN Serial Data Input. High impedance data input for the I2C serial interface bus. The LTC9105 uses two pins to implement the bidirectional SDA function to simplify isolation of the I2C bus. To implement a standard bidirectional SDA pin, tie SDAOUT and SDAIN together. Internally pulled up to BYP through a 50kΩ (typ.) resistor. See I2C Interface for more information. 16 AD0 I2C Chip Address Bit 0 Select. Use this pin to change the I2C chip address. Tie this pin to RTN to set I2C address bit AD0 to 0. Tie this pin to BYP to set bit AD0 of the I2C chip address to 1. Internally pulled down to RTN through a 50kΩ (typ.) resistor. See I2C Interface for more information. 17, 20 M[1:0] PoE Minimum Power Select. Use these pins to set the minimum number of Mark events required to enable the external MOSFET and power up the load. Tie high by connecting to BYP. Tie low by connecting to RTN. Internally pulled down to RTN through a 50kΩ (typ.) resistor. 18 BYP Internal Power Supply Bypass. Connect a 1μF ceramic capacitor between this pin and RTN. 7, 19, 21 (Exposed Pad) RTN PD Interface Return Rail. Pin 21 (Exposed Pad) must be connected to pin 7, pin 19, and PCB heat sink. 3, 12 NC No Connection. Not internally connected. |
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