LTC4292 datasheet(15/22 Pages) AD

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Data Sheet

LTC9105

I2C INTERFACE

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Rev. A | 15 of 22

Figure 19. Short Form I2C Multi-Byte Read

Figure 20. Long Form I2C Multi-Byte Read

Figure 21. I2C Write

Figure 22. I2C Interface Timing

I2C Interface Overview

The LTC9105 includes an I2C serial interface, enabling the PD's

application processor to read parametric telemetry, PSE allocated

power, and auxiliary input status; and to write power input priority.

See Table 10 for register details and descriptions.

Figure 22 presents the I2C interface timing parameters. These pa-

rameters are defined for the LTC9105 in Electrical Characteristics.

I2C Serial Address Byte

The LTC9105 chip address (bits [7:1] of the serial address byte) is

settable to 0x40 or 0x41, based on the AD0 pin setting. Tie AD0 to

RTN to set the chip address to 0x40, or tie AD0 to BYP to set the

chip address to 0x41.

I2C Read

There are two ways to read data from the I2C port on the LTC9105.

The LTC9105 responds to either a short form multi-byte read (Fig-

ure 19) or a long form multi-byte read (Figure 20). When reading

from the LTC9105 with a long form multi-byte read, always read

from register address 0x00.

I2C data is gathered from the LTC9105 in a single 5-byte read.

Reading multiple bytes in the same transaction ensures that para-

metric data is from the same ADC conversion. For example, the

current LSB and current MSB must be read concurrently to ensure

that the upper byte and lower byte values are from the same con-

version. Similarly, voltage (or power) and current read back must

LTC4292 Datasheet(PDF) 15 Page - Analog Devices