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Data Sheet

LTC9105

THEORY OF OPERATION

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Rev. A | 11 of 22

Table 7. PSE Allocated Power

PD Requested Class

pse_mark

PSE Allocated Power

Any

13W

Any

3.84W

Any

6.49W

Any

13W

00b

13W

01b, 10b, 11b

25.5W

00b

13W

01b

25.5W

10b, 11b

40W

00b

13W

01b

25.5W

10b, 11b

51W

00b

13W

01b

25.5W

10b

51W

11b

62W

00b

13W

01b

25.5W

10b

51W

11b

71.3W

Minimum Initial Required Power

IEEE compliance requires PDs to provide an active indication to

the user when a PSE allocates insufficient power through a PSE

behavior known as demotion. For PD applications that do not

support demotion, the LTC9105 can be configured to block the PD

application from powering up and to provide an indication.

To determine if the LTC9105 should apply power, the LTC9105

compares the number of mark events provided by the PSE to the

M1 and M0 pin settings. Connect pins M1 and M0 to BYP or

RTN according to Table 8 to configure the minimum initial required

power.

Table 8. Setting Minimum Initial Required Power

Initial Power

Requirement

M1 PIN

M0 PIN

pse_mark

MOSFET State

13W or less

RTN

Any

13W thru

25.5W

RTN

BYP

00b

OFF

01b, 10b, 11b

25.5W thru

51W

BYP

RTN

00b, 01b

OFF

10b, 11b

Greater than

51W

BYP

00b, 01b, 10b

OFF

11b

When insufficient power is allocated and the AUX pin is low, the

PWRGD pin sinks IPWRGD, the Hot Swap MOSFET is turned off,

and the LTC9105 draws minimal current (see Automatic Maintain

Power Signature) to keep the PoE input powered. The PWRGD pin

and MOSFET state can be combined as an indication of insufficient

power allocation.

Link Layer Discovery Protocol (LLDP) Power Negotiation

In PoE systems, after initial power-on, power may be renegotiated

through LLDP. The LTC9105 does not have access to Ethernet data

and does not react automatically to LLDP power negotiation, includ-

ing PWRGD pin state, MOSFET state, and seamless switchover

settings.

For seamless switchover applications, the application processor

may need to update the LTC9105's power priority mode when

renegotiating power through LLDP. See Dual-Input Prioritization.

Inrush and Power On

Once the PSE detects and classifies the PD, the PSE applies

power to the PD depending on the rules described in Dual-Input

Prioritization. When the port voltage rises above the VON threshold,

and the LTC9105 determines if the PSE allocated power is equal

or higher than the PD requested power, and if an auxiliary power

source is not present (through the aux_status bit), the LTC9105

drives the external MOSFET GATE pin so as to allow a 100mA

(typ) current to charge the external bulk capacitor. When the bulk

capacitor is fully charged and the MOSFET current drops below

100mA, the external MOSFET is fully enhanced. In the event the

external MOSFET does not enhance within 93.75ms (typ), inrush

times out.

When inrush times out, the MOSFET turns off and the Automatic

MPS feature is disabled. The PD remains in this state until the

port voltage drops below VOFF. See Automatic Maintain Power

Signature for further description of the Automatic MPS feature.

Power Good

The PWRGD pin is used to hold off the downstream circuitry until

inrush is complete and the external MOSFET is fully enhanced.

The PWRGD pin first sinks IPWRGD (250uA, typ.) starting when

the port voltage rises above VON and continuing for up to tPWRGD

(93.75ms, typ.), then enters a high impedance state to allow an

external PWRGD pull-up to assert the power good indication.

AUXILIARY INPUT

The AUX pin is used to detect when an auxiliary power supply is

attached. Figure 16 shows an example of an AUX sensing circuit.

When an auxiliary power supply is detected, aux_status is set

to 1. The LTC9105 MOSFET state (ON or OFF) is configurable,

based on stdby_dis and priority bit settings; see Dual-Input

Prioritization for seamless switchover options, example AUX sens-

ing circuit, and register configuration.

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