ADS1282IPWR datasheet(7/42 Pages) TI

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OVERVIEW

4th-Order

Modulator

Programmable

DigitalFilter

Serial

Interface

Calibration

Control

AINP1

AVSS

CLK

DVDD

DGND

DIN

DOUT

MCLK

DRDY

SCLK

AINN1

MFLAG

ADS1282

AINN2

AINP2

Over-Range

Detection

BYPAS

LDO

PGA

400W

AVDD+AVSS

400W

+1.8V

(Digitalcore)

300W

RESET

PWDN

SYNC

AVDD

ADS1282

SBAS418A – SEPTEMBER 2007 – REVISED DECEMBER 2007

The

inherently-stable,

fourth-order,

delta-sigma

The ADS1282 is a high-performance analog-to-digital

modulator measures the differential input signal

converter (ADC) intended for energy exploration,

VIN = (AINP – AINN) against the differential reference

seismic

monitoring,

chomatography,

and

other

VREF = (VREFP – VREFN). A digital output (MFLAG)

exacting applications. The converter provides 24- or

indicates that the modulator is in overload resulting

32-bit output data in data rates from 4000SPS to

from an overdrive condition. The modulator output is

250SPS.

available directly on the MCLK, M0, and M1 output

pins. The modulator connects to an on-chip digital

Figure 1 shows the block diagram of the ADS1282.

filter that provides the output code readings.

The device features unipolar and bipolar analog

power supplies (AVDD and AVSS, respectively) for

The digital filter is comprised of a variable decimation

input range flexibility and a digital supply accepting

rate, fifth-order sinc filter followed by a variable

1.8V to 3.3V. The analog supplies may be set to +5V

phase, decimate-by-32, finite impulse response (FIR)

to accept unipolar signals (with input offset) or set

low-pass filter with programmable phase, and then by

lower in the range of ±2.5V to accept true bipolar

an adjustable high-pass filter for dc removal of the

input signals (ground referenced).

output reading. The output of the digital filter can be

taken from the sinc, the FIR low-pass, or the infinite

An internal low dropout (LDO) regulator is used to

impulse response (IIR) high-pass sections.

supply the digital core from DVDD. The BYPAS pin is

the LDO output and requires a 0.1

µF capacitor for

Gain and offset registers scale the digital filter output

noise reduction (BYPAS should not be used to drive

to produce the final code value. The scaling feature

external circuitry).

can be used for calibration and sensor gain matching.

The output data word is provided as either a 24-bit

The 2-channel input MUX allows five configurations:

word or a

full

32-bit

word,

allowing

complete

Input 1; Input 2; Input 1 and Input 2 shorted together;

utilization of the inherently high resolution.

shorted with 400

Ω test; and common-mode test. The

input MUX is followed by a continuous time PGA,

The SYNC input resets the operation of both the

featuring very low noise of 4nV/

√Hz. The PGA is

digital

filter

and

the

modulator,

allowing

controlled by register settings, allowing gains of 1 to

synchronization conversions of multiple ADS1282

64.

devices to an external event. The SYNC input

supports a continuously-toggled input mode that

accepts an external data frame clock locked to the

conversion rate.

Figure 1. ADS1282 Block Diagram

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