ADS1282IPWR datasheet(13/42 Pages) TI

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DIGITAL FILTER

Sinc Filter Stage (sinx/x)

H(Z)=

-1

(3)

SincFilter

Decimateby

8to128

FIRFilter

Decimate

by32

High-Pass

Filter

(IIR)

Filter

MUX

ToCalibrationBlock

FromModulator

DirectModulator

BitStream

ADS1282

SBAS418A – SEPTEMBER 2007 – REVISED DECEMBER 2007

Table 5. Digital Filter Selection, Pin Mode

MOD/DIN

HPF/SYNC

The digital filter receives the modulator output and

DIGITAL FILTERS SELECTED

decimates the data stream. By adjusting the amount

Bypass; modulator output mode

of filtering, tradeoffs can be made between resolution

and data rate: filter more for higher resolution, filter

Sinc + FIR

less for higher data rate.

Sinc + FIR + HPF

(low-pass and high-pass)

The digital filter is comprised of three cascaded filter

stages: a variable-decimation, fifth-order sinc filter; a

fixed-decimation

FIR,

low-pass

filter

(LPF)

with

selectable phase; and a programmable, first-order,

The sinc filter is a variable decimation rate, fifth-order,

high-pass filter (HPF), as shown in Figure 11.

low-pass filter. Data are supplied to this section of the

filter from the modulator at the rate of fMOD (fCLK/4).

The output can be taken from one of the three filter

The sinc filter attenuates the high-frequency noise of

blocks, as Figure 11 shows. To implement the digital

the modulator, then decimates the data stream into

filter completely off-chip, select the filter bypass

parallel data. The decimation rate affects the overall

setting (modulator output). For partial filtering by the

data rate of the converter; it is set by the DR[1:0] and

ADS1282, select the sinc filter output. For complete

MODE selections, as shown in Table 6.

on-chip filtering, activate both the sinc and FIR

stages. The HPF can then be included to remove dc

Equation 3 shows the scaled Z-domain transfer

and low frequencies from the data. Table 4 shows the

function of the sinc filter.

filter options in Register mode. Table 5 shows the

filter options in Pin mode.

Table 4. Digital Filter Selection, Register Mode

FILTR[1:0] BITS

DIGITAL FILTERS SELECTED

Bypass; modulator output mode

Sinc

Sinc + FIR

Sinc + FIR + HPF

(low-pass and high-pass)

Figure 11. Digital Filter

Table 6. Sinc Filter Data Rates (CLK = 4.096MHz)

DR[1:0] PINS

DR[2:0] REGISTER

DECIMATION RATIO (N)

SINC DATA RATE (SPS)

000

128

8,000

001

16,000

010

32,000

011

64,000

—

100

128,000

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