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RESET (RESET Pin and Reset Command)

DRDY

t

DR

Wakeup

Command

POWER-ON SEQUENCE

SystemClock

(f

)

CLK

DRDY

RESETPin

RESETCommand

t

RST

Settled

Data

or

t

CRHD

t

DR

t

RCSU

POWER-DOWN

CLK

DVDD

DRDY

InternalReset

1Vnom

AVDD

AVSS

-

3.5Vnom

2

16

t

DR

f

CLK

ADS1282

SBAS418A – SEPTEMBER 2007 – REVISED DECEMBER 2007

In power-down, note that the device outputs remain

active and the device inputs must not float. When the

The ADS1282 may be reset in two ways: toggle the

Standby command is sent, the SPI port and the

RESET pin low or send a Reset command. When

configuration registers are kept active. Figure 25 and

using the RESET pin, take it low and hold for at least

Table 12 show the timing.

until the pin is released. By command, RESET takes

rising edge of SCLK of the command. Note: to ensure

that the Reset command can function, the SPI

interface may require a reset; see the Serial Interface

section.

In reset, registers are set to default and the

conversions are synchronized on the next rising edge

of CLK. New conversion data are available, as shown

Figure 25. PWDN Pin and Wake-Up Command

in Figure 24 and Table 11.

Timing

The ADS1282 has three power supplies: AVDD,

AVSS, and DVDD. Figure 26 shows the power-on

sequence of the ADS1282. The power supplies can

be sequenced in any order. The supplies [the

difference of (AVDD – AVSS) and DVDD] generate

an internal reset whose outputs are summed to

generate a global internal reset. After the supplies

Figure 24. Reset Timing

are counted before releasing the internal reset. After

the internal reset is released, new conversion data

Table 11. Reset Timing for Figure 24

are available, as shown in Figure 26 and Table 12.

PARAMETER DESCRIPTION

MIN

UNITS

CLK to RESET hold time

10

ns

RESET to CLK setup time

10

ns

RESET low

2

62.98046875/

Time for data ready

(PWDN Pin and Standby Command)

There are two ways to power-down the ADS1282:

take the PWDN pin low or send a Standby command.

When the PWDN pin is pulled low, the internal

Figure 26. Power-On Sequence

circuitry is disabled to minimize power and the

contents of the register settings are reset.

Table 12. Power-On, PWDN Pin, and Wake-Up Command Timing for New Data

PARAMETER

DESCRIPTION

FILTER MODE

See Appendix, Table 24

and new data ready after PWDN pin or Wake-Up command

(2)

FIR

(1)

Supply power-on and PWDN pin default is 1000SPS FIR.

(2)

Subtract two CLK cycles for the Wake-Up command. The Wake-Up command is timed from the next rising edge of CLK to after the

eighth rising edge of SCLK during command to DRDY falling.

Copyright © 2007, Texas Instruments Incorporated

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