ADS1282IPWR datasheet(12/42 Pages) TI

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MODULATOR OUTPUT MODE

MOD/2

MFLAG

100%FS

AINN

AINP

IABSI

MFLAG

+100%

(AINP

AINN)

-100%

CLK

SYNC

PHS/MCLK

DR0/M0

DR1/M1

MCM0, 1

(MCLK=CLK/4)

SCSU

CSHD

CMD

SYMD

ADS1282

SBAS418A – SEPTEMBER 2007 – REVISED DECEMBER 2007

Figure 8 and Figure 9 illustrate, the absolute value of

the input is compared to 100% of range. The output

The modulator digital stream output is available

of the comparator is sampled at the rate of fMOD/2,

directly, bypassing and disabling the internal digital

yielding the MFLAG output. The minimum MFLAG

filter. The modulator output mode is activated in the

pulse width is fMOD/2.

Pin mode by setting MOD/DIN = 1, and in Register

mode

setting

the

CONFIG0

bits

FILTR[1:0] = 00. Pins DR0/M0 and DR1/M1 then

become

the

modulator

data

outputs

and

the

PHS/MCLK becomes the modulator clock output.

When not in the modulator mode, these pins are

inputs and must not float.

The modulator output is composed of three signals:

one output for the modulator clock (PHS/MCLK) and

two outputs for the modulator data (DR0/M0 and

Figure 8. Modulator Over-Range Block Diagram

DR1/M1). The modulator clock output rate is fMOD

(fCLK/4). The SYNC input resets the MODCLK phase,

as shown in Figure 10. The SYNC input is latched on

the rising edge of CLK. The MODCLK resets and the

next rising edge of MODCLK occurs five CLK periods

later.

The modulator output data are two bits wide, which

must be merged together before being filtered. Use

the time domain equation of Equation 2 to merge the

data outputs.

Figure 9. Modulator Over-Range Flag Operation

Figure 10. Modulator Mode Timing

Modulator Output Timing for Figure 10

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

tMCD0, 1

MODCLK rising edge to M0, M1 valid propagation delay(1)

100

CLK rising edge (after SYNC rising edge) to MODCLK rising edge

tCMD

1/fCLK

reset time

tCSHD

CLK to SYNC hold time to not latch on CLK edge

tSCSU

SYNC to CLK setup time to latch on CLK edge

tSYMD

SYNC to stable bit stream

1/fMOD

(1)

Load on M0 and M1 = 20pF || 100k

Ω.

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