ADS1282IPWR datasheet(21/42 Pages) TI

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Data Ready (DRDY)

DATA FORMAT

REF

SCLK

DRDY

DOUT

Bit31

Bit30

Bit29

REF

-VREF

DRDY

DataUpdating

4/f

CLK

ADS1282

SBAS418A – SEPTEMBER 2007 – REVISED DECEMBER 2007

DRDY is an output; when it transitions low, this

The ADS1282 provides 32 bits of conversion data in

transition indicates new conversion data are ready, as

binary

twos

complement

format,

shown

shown in Figure 29. When reading data by the

Table 13. The LSB of the data is a redundant sign bit:

continuous mode, the data must be read within four

'0' for positive numbers and '1' for negative numbers.

CLK periods before DRDY goes low again or the data

However, when the output is clipped to +FS, the

are overwritten with new conversion data. When

LSB = 1; when the output is clipped to –FS, the

reading data by the command mode, the read

LSB = 0. If desired, the data readback may be

operation can overlap the occurrence of the next

stopped at 24 bits.

DRDY without data corruption.

Table 13. Ideal Output Code versus Input Signal

INPUT SIGNAL VIN

32-BIT IDEAL OUTPUT

(AINP – AINN)

CODE(1)

7FFFFFFFh

7FFFFFFEh

Figure 29. DRDY with Data Retrieval

00000002h

00000000h

DRDY resets high on the first falling edge of SCLK.

Figure 29 and Figure 30 show the function of DRDY

with and without data readback, respectively.

FFFFFFFFh

If data are not retrieved (no SCLK provided), DRDY

pulses high for four fCLK periods during the update

80000001h

time, as shown in Figure 30.

80000000h

(1) Excludes effects of noise, linearity, offset, and gain errors.

Figure 30. DRDY With No Data Retrieval

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