Technical Reference Notes (TRN)

AA10C Series

36 Vdc to 75 Vdc Inputs, 10 W

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ASTEC POWER - Andover

7 of 12

Figure 8. Typical Output Voltage Startup

Figure 9. Typical Output Ripple

Vi = Vi,nom, Io = Io,max.

Vi = Vi,nom, Io = Io,max.

Normalized Output Voltage

Time (100 us/div)

Time (100 us/div)

Figure 10. Typical Dynamic Response

Figure 11. Typical Dynamic Response

Step Load Change from 50% to 75% Io,max

Step Load Change from 50% to 25% Io,max

Test Configurations

Note: Measure input reflected-ripple current with a simulated source inductance (Ltest) of 12 uH. Capacitor

Cs offsets possible battery impedance. Measure current as shown above.

Figure 12. Input Reflected-ripple Test Setup.

BATTERY

Cs 220 uF

ESR < 0.1 OHM

@ 20 ºC, 100 kHz

Ltest

12 uH

33 uF

ESR < 0.7 OHM

@ 20 ºC, 100 kHz

Vi(+)

Vi(-)

TO OSCILLOSCOPE