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HMC7044 Datasheet(PDF) 6 Page - Analog Devices

Part # HMC7044
Description  Evaluating the HMC7044 Dual Loop Clock Jitter Cleaner
PDF  10 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

HMC7044 Datasheet(HTML) 6 Page - Analog Devices

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UG-826
EK1HMC7044LP10B User Guide
Rev. 0 | Page 6 of 10
USING THE SOFTWARE TO CONTROL THE
FUNCTIONAL BLOCKS OF THE HMC7044
Register W/R
The update icon issues a GUI update command by reading all
registers and setting every widget according to read values.
Figure 8. Update Icon
GPIO Controls
The GPIO tab allows the user to control general-purpose
input/output to monitor the alarms/status indicators to
determine the health of the system.
Four GPIO configurations can be controlled from this tab
(see Figure 7).
PLL1 Controls
The PLL1 tab in the main window (see Figure 9) allows the user
to configure the PLL1 parameters.
Figure 9. PLL1 Tab of HMC7044 Evaluation Software GUI
The PLL1 input buffer controls are located on the left side of
the PLL1 tab (see Figure 10). Enable/disable, termination type,
ac coupling, and dc coupling options can be controlled.
The PLL1 input/VCXO prescalers are shown in Figure 11.
Divide ratios of these five prescalers are controllable from this
section. The priority table of PLL1 references are also located in
the INPUT Priority section of this tab.
The PLL1 reference and feedback divider ratios, PFD polarity,
and charge pump current setting controls are shown in Figure 12.
Additional control bits of PLL1 are located at the bottom of the
PLL1
tab, as shown in Figure 13. See the HMC7044 datasheet
for further details on these bits.
Figure 10. PLL1 Input Buffers
Figure 11. PLL1 Input/VCXO Prescalers and Reference MUX
Figure 12. PLL1 Reference and Feedback Divider and Charge Pump



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