EK1HMC7044LP10B User Guide

UG-826

Rev. 0 | Page 7 of 10

Figure 13. PLL1 Additional Control Bits

PLL 2 CONTROLS

The PLL 2 tab in the main window (see Figure 14) allows the

user to configure the PLL2 parameters.

Figure 14. PLL2 Tab of HMC7044 Evaluation Software GUI

The PLL2 reference and feedback divider ratios, PFD polarity,

and charge pump current setting controls are shown in Figure 15.

Figure 15. PLL2 Reference and Feedback Divider and Charge Pump

The PLL2 VCO MUX for selecting internal or external VCO is

shown in Figure 16.

Figure 16. PLL2 Internal External VCO selection

The PLL2 input/OSCOUTx/OSCOUTx divider is shown in

Figure 17. The divide ratio of these outputs are controllable

from this section.

Figure 17. OSCOUTx/OSCOUTx Path

Additional control bits of the PLL2 are located at the bottom of

the PLL2 tab, as shown in Figure 18. See the HMC7044 data

sheet for further details on these bits.

Figure 18. PLL2 Additional Control Bits