ACT8865 datasheet(23/32 Pages) QORVO

23 / 32 page

ACT8865

Advanced PMU for Atmel SAMA5Dx Series & SAM9 Series Processors

Data Sheet Rev. H, September 2019 | Subject to change without notice

23 of 32

www.qorvo.com

Control Sequences

The ACT8865 features a variety of control sequences that

are optimized for supporting system enable and disable

sequences

Atmel

SAMA5D2,

SAMA5D3

Series:

SAMA5D[31/33/34/35/36]

and

SAM9

series:

SAM9G[15/25/35/45/46], SAM9X[25/35], SAM9M[10/11],

SAM9N[11/12] application processor.

Enabling/Disabling Sequence

A typical enable sequence is initiated whenever nPBIN is

asserted low via 50KΩ resistance. The enable

sequence begins by enabling REG3/REG5. When

REG3/REG5 reaches its power-OK threshold, nRSTO

is asserted low, resetting the microprocessor. When

REG3/REG5 reaches its power-OK threshold for 2ms,

REG1 is enabled. When REG3/REG5 reaches its

power-OK threshold for 4ms, REG2 is enabled. When

REG3/REG5 reaches its power-OK threshold for 8ms,

REG4 is enabled. When REG3 is above its power-OK

threshold when the reset timer expires, nRSTO is de-

asserted, allowing the microprocessor to begin its boot

sequence. REG6 and REG7 can be enabled or

disabled by PWREN after system powers up.

During the boot sequence, the microprocessor must

assert PWRHLD, holding the regulators to ensure that

the system remains powered after nPBIN is released.

As with the enable sequence, a typical disable

sequence is initiated when the user presses the push-

button, which interrupts the processor via the nPBSTAT

output. The actual disable sequence is completely

software-controlled, but typically involved initiating

various “clean-up” processes before finally set

MSTROFF[] bit to 1 to shut the system down.

Figure 3:

Enable/Disable Sequence for ACT8865QI305-T and

ACT8865QI405-T

: Typical value shown, actual delay time may vary from (T-1ms) x

88% to T x 112%, where T is the typical delay time setting.

ACT8865 Datasheet(PDF) 23 Page - Qorvo, Inc

ACT8865 Datasheet(HTML) 23 Page - Qorvo, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL