ACT8865 datasheet(27/32 Pages) QORVO

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ACT8865

Advanced PMU for Atmel SAMA5Dx Series & SAM9 Series Processors

Data Sheet Rev. H, September 2019 | Subject to change without notice

27 of 32

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LOW-NOISE, LOW-DROPOUT LINEAR REGULATORS

General Description

REG4, REG5, REG6 and REG7 are low-noise, low-

dropout linear regulators (LDOs) that supply up to

320mA. Each LDO has been optimized to achieve low

noise and high-PSRR, achieving more than 65dB PSRR

at frequencies up to 10kHz.

Output Current Limit

Each LDO contains current-limit circuitry featuring a

current-limit fold-back function. During normal and

moderate

overload

conditions,

the

regulators

can

support more than their rated output currents. During

extreme overload conditions, however, the current limit

is reduced by approximately 30%, reducing power

dissipation within the IC.

Compensation

The LDOs are internally compensated and require very

little design effort, simply select input and output

capacitors according to the guidelines below.

Input Capacitor Selection

Each LDO requires a small 1μF ceramic output

capacitor for stability. For best performance, each

output capacitor should be connected directly between

the output and GA pins, as close to the output as

possible, and with a short, direct connection. High

quality ceramic capacitors such as X7R and

X5R

dielectric types are strongly recommended.

Output Capacitor Selection

Each LDO requires a small 3.3μF ceramic output

capacitor for stability. For best performance, each

output capacitor should be connected directly between

the output and GA pins, as close to the output as

possible, and with a short, direct connection. High

quality ceramic capacitors such as X7R and X5R

dielectric types are strongly recommended.

Configuration Options

Output Voltage Programming

By default, each LDO powers up and regulates to its

default output voltage. Once the system is enabled,

each output voltage may be independently programmed

to a different value by writing to the

regulator's VSET[ ] register via the I

2C serial interface as

shown in Table 4.

Enable

Disable

Control

During normal operation, each LDO may be enabled or

disabled via I2C interface by writing to that

regulator's ON[] bit. The regulator accepts rising or

falling edge of ON[] bit as on/off signal. To enable the

regulator, clear ON[] to 0 first then set to 1. To disable the

regulator, set ON[] to 1 first then clear it to 0.

REG4, REG5, REG6, REG7 Turn-on Delay

Each of REG4, REG5, REG6 and REG7 features a

programmable Turn-on Delay which help ensure a

reliable qualification. This delay is programmed by

DELAY[2:0], as shown in Table 5.

Table 5:

REGx/DELAY[ ] Turn-On Delay

DELAY[2] DELAY[1] DELAY[0] TURN-ON DELAY

0 ms

2 ms

4 ms

8 ms

16 ms

32 ms

64 ms

128 ms

Output Discharge

Each of the ACT8865’s LDOs features an optional

output discharge function, which discharges the output

to ground through a 1.5kΩ resistance when the LDO is

disabled. This feature may be enabled or disabled by

setting DIS[ ] via; set DIS[ ] to 1 to enable this function,

clear DIS[ ] to 0 to disable it.

Low-Power Mode

Each of ACT8865's LDOs features a LOWIQ[ ] bit

which, when set to 1, reduces the LDO's quiescent

current by about 16%, saving power and extending

battery lifetime.

OK[ ] and Output Fault Interrupt

Each LDO features a power-OK status bit that can be

read by the system microprocessor via the interface. If

an output voltage is lower than the power-OK threshold,

typically

11%

below

the

programmed

regulation

voltage, the value of that regulator's OK[ ] bit will be 0.

If a LDO's nFLTMSK[ ] bit is set to 1, the ACT8865 will

interrupt the processor if that LDO's output voltage falls

below the power-OK threshold. In this case, nIRQ will

assert low and remain asserted until

the OK[ ] bit has been read via I

2C.

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