AX88190AL datasheet(16/49 Pages) ASIX

16 / 49 page

AX88190A

PCMCIA Fast Ethernet MAC Controller

ASIX ELECTRONICS CORPORATION

4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write)

FIELD

R/W/C

DESCRIPTION

7:3

Reserved

R/W

PPwrDwn : PHY power down setting

While this bit set to 1, PPWDN pin (pin 114) will be active to force PHY chip into power

down mode. As for PPWDN is active high or active low. Please refer section 2.7 Power on

configuration setup signal cross reference table.

Intr : Interrupt Request

The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it

is not request interrupt service.

IntrAck : Interrupt Acknowledge

This bit will be 0. The Intr will reflect the status of interrupt requesting.

4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write)

The I/O Base registers (LIOBASE0 and LIOBASE1) determine the base address of the I/O range used to

access the LAN specific registers (MAC Core Registers).

I/O Base Register 0

FIELD

R/W/C

DESCRIPTION

7:0

R/W

Base I/O address bit 7 – 0.

I/O Base Register 1

FIELD

R/W/C

DESCRIPTION

7:0

R/W

Base I/O address bit 15 – 8.

AX88190AL Datasheet(PDF) 16 Page - ASIX Electronics Corporation